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      1 // SPDX-License-Identifier: GPL-2.0+
      2 /*
      3  * (C) Copyright 2012
      4  * eInfochips Ltd. <www.einfochips.com>
      5  * Written-by: Ajay Bhargav <contact (at) 8051projects.net>
      6  *
      7  * (C) Copyright 2009
      8  * Marvell Semiconductor <www.marvell.com>
      9  */
     10 
     11 #include <common.h>
     12 #include <asm/io.h>
     13 #include <usb.h>
     14 #include <asm/arch/cpu.h>
     15 #include <asm/arch/armada100.h>
     16 #include <asm/arch/utmi-armada100.h>
     17 
     18 static int utmi_phy_init(void)
     19 {
     20 	struct armd1usb_phy_reg *phy_regs =
     21 		(struct armd1usb_phy_reg *)UTMI_PHY_BASE;
     22 	int timeout;
     23 
     24 	setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
     25 	udelay(1000);
     26 	setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
     27 
     28 	clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
     29 	setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
     30 
     31 	setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
     32 
     33 	/* Calibrate pll */
     34 	timeout = 10000;
     35 	while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
     36 		;
     37 	if (!timeout)
     38 		return -1;
     39 
     40 	udelay(200);
     41 	setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
     42 	udelay(400);
     43 	clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
     44 
     45 	udelay(200);
     46 	setbits_le32(&phy_regs->utmi_tx, RCAL_START);
     47 	udelay(400);
     48 	clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
     49 
     50 	timeout = 10000;
     51 	while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
     52 		;
     53 	if (!timeout)
     54 		return -1;
     55 
     56 	return 0;
     57 }
     58 
     59 /*
     60  * Initialize USB host controller's UTMI Physical interface
     61  */
     62 int utmi_init(void)
     63 {
     64 	struct armd1mpmu_registers *mpmu_regs =
     65 		(struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
     66 
     67 	struct armd1apmu_registers *apmu_regs =
     68 		(struct armd1apmu_registers *)ARMD1_APMU_BASE;
     69 
     70 	/* Turn on 26Mhz ref clock for UTMI PLL */
     71 	setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
     72 
     73 	/* USB Clock reset */
     74 	writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
     75 	writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
     76 
     77 	/* Initialize UTMI transceiver */
     78 	return utmi_phy_init();
     79 }
     80