1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * 5 * Author: Donghwa Lee <dh09.lee (at) samsung.com> 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <common.h> 11 #include <display.h> 12 #include <fdtdec.h> 13 #include <linux/libfdt.h> 14 #include <malloc.h> 15 #include <video_bridge.h> 16 #include <linux/compat.h> 17 #include <linux/err.h> 18 #include <asm/arch/clk.h> 19 #include <asm/arch/cpu.h> 20 #include <asm/arch/dp_info.h> 21 #include <asm/arch/dp.h> 22 #include <asm/arch/pinmux.h> 23 #include <asm/arch/power.h> 24 25 #include "exynos_dp_lowlevel.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 static void exynos_dp_disp_info(struct edp_disp_info *disp_info) 30 { 31 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + 32 disp_info->h_back_porch + disp_info->h_front_porch; 33 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + 34 disp_info->v_back_porch + disp_info->v_front_porch; 35 36 return; 37 } 38 39 static int exynos_dp_init_dp(struct exynos_dp *regs) 40 { 41 int ret; 42 exynos_dp_reset(regs); 43 44 /* SW defined function Normal operation */ 45 exynos_dp_enable_sw_func(regs, DP_ENABLE); 46 47 ret = exynos_dp_init_analog_func(regs); 48 if (ret != EXYNOS_DP_SUCCESS) 49 return ret; 50 51 exynos_dp_init_hpd(regs); 52 exynos_dp_init_aux(regs); 53 54 return ret; 55 } 56 57 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) 58 { 59 int i; 60 unsigned char sum = 0; 61 62 for (i = 0; i < EDID_BLOCK_LENGTH; i++) 63 sum = sum + edid_data[i]; 64 65 return sum; 66 } 67 68 static unsigned int exynos_dp_read_edid(struct exynos_dp *regs) 69 { 70 unsigned char edid[EDID_BLOCK_LENGTH * 2]; 71 unsigned int extend_block = 0; 72 unsigned char sum; 73 unsigned char test_vector; 74 int retval; 75 76 /* 77 * EDID device address is 0x50. 78 * However, if necessary, you must have set upper address 79 * into E-EDID in I2C device, 0x30. 80 */ 81 82 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ 83 exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR, 84 EDID_EXTENSION_FLAG, &extend_block); 85 86 if (extend_block > 0) { 87 printf("DP EDID data includes a single extension!\n"); 88 89 /* Read EDID data */ 90 retval = exynos_dp_read_bytes_from_i2c(regs, 91 I2C_EDID_DEVICE_ADDR, 92 EDID_HEADER_PATTERN, 93 EDID_BLOCK_LENGTH, 94 &edid[EDID_HEADER_PATTERN]); 95 if (retval != 0) { 96 printf("DP EDID Read failed!\n"); 97 return -1; 98 } 99 sum = exynos_dp_calc_edid_check_sum(edid); 100 if (sum != 0) { 101 printf("DP EDID bad checksum!\n"); 102 return -1; 103 } 104 105 /* Read additional EDID data */ 106 retval = exynos_dp_read_bytes_from_i2c(regs, 107 I2C_EDID_DEVICE_ADDR, 108 EDID_BLOCK_LENGTH, 109 EDID_BLOCK_LENGTH, 110 &edid[EDID_BLOCK_LENGTH]); 111 if (retval != 0) { 112 printf("DP EDID Read failed!\n"); 113 return -1; 114 } 115 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); 116 if (sum != 0) { 117 printf("DP EDID bad checksum!\n"); 118 return -1; 119 } 120 121 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, 122 &test_vector); 123 if (test_vector & DPCD_TEST_EDID_READ) { 124 exynos_dp_write_byte_to_dpcd(regs, 125 DPCD_TEST_EDID_CHECKSUM, 126 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); 127 exynos_dp_write_byte_to_dpcd(regs, 128 DPCD_TEST_RESPONSE, 129 DPCD_TEST_EDID_CHECKSUM_WRITE); 130 } 131 } else { 132 debug("DP EDID data does not include any extensions.\n"); 133 134 /* Read EDID data */ 135 retval = exynos_dp_read_bytes_from_i2c(regs, 136 I2C_EDID_DEVICE_ADDR, 137 EDID_HEADER_PATTERN, 138 EDID_BLOCK_LENGTH, 139 &edid[EDID_HEADER_PATTERN]); 140 141 if (retval != 0) { 142 printf("DP EDID Read failed!\n"); 143 return -1; 144 } 145 sum = exynos_dp_calc_edid_check_sum(edid); 146 if (sum != 0) { 147 printf("DP EDID bad checksum!\n"); 148 return -1; 149 } 150 151 exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST, 152 &test_vector); 153 if (test_vector & DPCD_TEST_EDID_READ) { 154 exynos_dp_write_byte_to_dpcd(regs, 155 DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]); 156 exynos_dp_write_byte_to_dpcd(regs, 157 DPCD_TEST_RESPONSE, 158 DPCD_TEST_EDID_CHECKSUM_WRITE); 159 } 160 } 161 162 debug("DP EDID Read success!\n"); 163 164 return 0; 165 } 166 167 static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs, 168 struct exynos_dp_priv *priv) 169 { 170 unsigned char buf[12]; 171 unsigned int ret; 172 unsigned char temp; 173 unsigned char retry_cnt; 174 unsigned char dpcd_rev[16]; 175 unsigned char lane_bw[16]; 176 unsigned char lane_cnt[16]; 177 178 memset(dpcd_rev, 0, 16); 179 memset(lane_bw, 0, 16); 180 memset(lane_cnt, 0, 16); 181 memset(buf, 0, 12); 182 183 retry_cnt = 5; 184 while (retry_cnt) { 185 /* Read DPCD 0x0000-0x000b */ 186 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12, 187 buf); 188 if (ret != EXYNOS_DP_SUCCESS) { 189 if (retry_cnt == 0) { 190 printf("DP read_byte_from_dpcd() failed\n"); 191 return ret; 192 } 193 retry_cnt--; 194 } else 195 break; 196 } 197 198 /* */ 199 temp = buf[DPCD_DPCD_REV]; 200 if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11) 201 priv->dpcd_rev = temp; 202 else { 203 printf("DP Wrong DPCD Rev : %x\n", temp); 204 return -ENODEV; 205 } 206 207 temp = buf[DPCD_MAX_LINK_RATE]; 208 if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70) 209 priv->lane_bw = temp; 210 else { 211 printf("DP Wrong MAX LINK RATE : %x\n", temp); 212 return -EINVAL; 213 } 214 215 /* Refer VESA Display Port Standard Ver1.1a Page 120 */ 216 if (priv->dpcd_rev == DP_DPCD_REV_11) { 217 temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f; 218 if (buf[DPCD_MAX_LANE_COUNT] & 0x80) 219 priv->dpcd_efc = 1; 220 else 221 priv->dpcd_efc = 0; 222 } else { 223 temp = buf[DPCD_MAX_LANE_COUNT]; 224 priv->dpcd_efc = 0; 225 } 226 227 if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 || 228 temp == DP_LANE_CNT_4) { 229 priv->lane_cnt = temp; 230 } else { 231 printf("DP Wrong MAX LANE COUNT : %x\n", temp); 232 return -EINVAL; 233 } 234 235 ret = exynos_dp_read_edid(regs); 236 if (ret != EXYNOS_DP_SUCCESS) { 237 printf("DP exynos_dp_read_edid() failed\n"); 238 return -EINVAL; 239 } 240 241 return ret; 242 } 243 244 static void exynos_dp_init_training(struct exynos_dp *regs) 245 { 246 /* 247 * MACRO_RST must be applied after the PLL_LOCK to avoid 248 * the DP inter pair skew issue for at least 10 us 249 */ 250 exynos_dp_reset_macro(regs); 251 252 /* All DP analog module power up */ 253 exynos_dp_set_analog_power_down(regs, POWER_ALL, 0); 254 } 255 256 static unsigned int exynos_dp_link_start(struct exynos_dp *regs, 257 struct exynos_dp_priv *priv) 258 { 259 unsigned char buf[5]; 260 unsigned int ret = 0; 261 262 debug("DP: %s was called\n", __func__); 263 264 priv->lt_info.lt_status = DP_LT_CR; 265 priv->lt_info.ep_loop = 0; 266 priv->lt_info.cr_loop[0] = 0; 267 priv->lt_info.cr_loop[1] = 0; 268 priv->lt_info.cr_loop[2] = 0; 269 priv->lt_info.cr_loop[3] = 0; 270 271 /* Set sink to D0 (Sink Not Ready) mode. */ 272 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE, 273 DPCD_SET_POWER_STATE_D0); 274 if (ret != EXYNOS_DP_SUCCESS) { 275 printf("DP write_dpcd_byte failed\n"); 276 return ret; 277 } 278 279 /* Set link rate and count as you want to establish */ 280 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); 281 exynos_dp_set_lane_count(regs, priv->lane_cnt); 282 283 /* Setup RX configuration */ 284 buf[0] = priv->lane_bw; 285 buf[1] = priv->lane_cnt; 286 287 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf); 288 if (ret != EXYNOS_DP_SUCCESS) { 289 printf("DP write_dpcd_byte failed\n"); 290 return ret; 291 } 292 293 exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0, 294 priv->lane_cnt); 295 296 /* Set training pattern 1 */ 297 exynos_dp_set_training_pattern(regs, TRAINING_PTN1); 298 299 /* Set RX training pattern */ 300 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1; 301 302 buf[1] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 303 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 304 buf[2] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 305 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 306 buf[3] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 307 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 308 buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 | 309 DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0; 310 311 ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 312 5, buf); 313 if (ret != EXYNOS_DP_SUCCESS) { 314 printf("DP write_dpcd_byte failed\n"); 315 return ret; 316 } 317 318 return ret; 319 } 320 321 static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs) 322 { 323 unsigned int ret; 324 325 exynos_dp_set_training_pattern(regs, DP_NONE); 326 327 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 328 DPCD_TRAINING_PATTERN_DISABLED); 329 if (ret != EXYNOS_DP_SUCCESS) { 330 printf("DP request_link_training_req failed\n"); 331 return -EAGAIN; 332 } 333 334 return ret; 335 } 336 337 static unsigned int exynos_dp_enable_rx_to_enhanced_mode( 338 struct exynos_dp *regs, unsigned char enable) 339 { 340 unsigned char data; 341 unsigned int ret; 342 343 ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET, 344 &data); 345 if (ret != EXYNOS_DP_SUCCESS) { 346 printf("DP read_from_dpcd failed\n"); 347 return -EAGAIN; 348 } 349 350 if (enable) 351 data = DPCD_ENHANCED_FRAME_EN | DPCD_LN_COUNT_SET(data); 352 else 353 data = DPCD_LN_COUNT_SET(data); 354 355 ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data); 356 if (ret != EXYNOS_DP_SUCCESS) { 357 printf("DP write_to_dpcd failed\n"); 358 return -EAGAIN; 359 360 } 361 362 return ret; 363 } 364 365 static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs, 366 unsigned char enhance_mode) 367 { 368 unsigned int ret; 369 370 ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode); 371 if (ret != EXYNOS_DP_SUCCESS) { 372 printf("DP rx_enhance_mode failed\n"); 373 return -EAGAIN; 374 } 375 376 exynos_dp_enable_enhanced_mode(regs, enhance_mode); 377 378 return ret; 379 } 380 381 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs, 382 struct exynos_dp_priv *priv, 383 unsigned char *status) 384 { 385 unsigned int ret, i; 386 unsigned char buf[2]; 387 unsigned char lane_stat[DP_LANE_CNT_4] = {0,}; 388 unsigned char shift_val[DP_LANE_CNT_4] = {0,}; 389 390 shift_val[0] = 0; 391 shift_val[1] = 4; 392 shift_val[2] = 0; 393 shift_val[3] = 4; 394 395 ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2, 396 buf); 397 if (ret != EXYNOS_DP_SUCCESS) { 398 printf("DP read lane status failed\n"); 399 return ret; 400 } 401 402 for (i = 0; i < priv->lane_cnt; i++) { 403 lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f; 404 if (lane_stat[0] != lane_stat[i]) { 405 printf("Wrong lane status\n"); 406 return -EINVAL; 407 } 408 } 409 410 *status = lane_stat[0]; 411 412 return ret; 413 } 414 415 static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs, 416 unsigned char lane_num, unsigned char *sw, unsigned char *em) 417 { 418 unsigned int ret; 419 unsigned char buf; 420 unsigned int dpcd_addr; 421 unsigned char shift_val[DP_LANE_CNT_4] = {0, 4, 0, 4}; 422 423 /* lane_num value is used as array index, so this range 0 ~ 3 */ 424 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); 425 426 ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf); 427 if (ret != EXYNOS_DP_SUCCESS) { 428 printf("DP read adjust request failed\n"); 429 return -EAGAIN; 430 } 431 432 *sw = ((buf >> shift_val[lane_num]) & 0x03); 433 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; 434 435 return ret; 436 } 437 438 static int exynos_dp_equalizer_err_link(struct exynos_dp *regs, 439 struct exynos_dp_priv *priv) 440 { 441 int ret; 442 443 ret = exynos_dp_training_pattern_dis(regs); 444 if (ret != EXYNOS_DP_SUCCESS) { 445 printf("DP training_pattern_disable() failed\n"); 446 priv->lt_info.lt_status = DP_LT_FAIL; 447 } 448 449 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); 450 if (ret != EXYNOS_DP_SUCCESS) { 451 printf("DP set_enhanced_mode() failed\n"); 452 priv->lt_info.lt_status = DP_LT_FAIL; 453 } 454 455 return ret; 456 } 457 458 static int exynos_dp_reduce_link_rate(struct exynos_dp *regs, 459 struct exynos_dp_priv *priv) 460 { 461 int ret; 462 463 if (priv->lane_bw == DP_LANE_BW_2_70) { 464 priv->lane_bw = DP_LANE_BW_1_62; 465 printf("DP Change lane bw to 1.62Gbps\n"); 466 priv->lt_info.lt_status = DP_LT_START; 467 ret = EXYNOS_DP_SUCCESS; 468 } else { 469 ret = exynos_dp_training_pattern_dis(regs); 470 if (ret != EXYNOS_DP_SUCCESS) 471 printf("DP training_patter_disable() failed\n"); 472 473 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); 474 if (ret != EXYNOS_DP_SUCCESS) 475 printf("DP set_enhanced_mode() failed\n"); 476 477 priv->lt_info.lt_status = DP_LT_FAIL; 478 } 479 480 return ret; 481 } 482 483 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs, 484 struct exynos_dp_priv *priv) 485 { 486 unsigned int ret; 487 unsigned char lane_stat; 488 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0, }; 489 unsigned int i; 490 unsigned char adj_req_sw; 491 unsigned char adj_req_em; 492 unsigned char buf[5]; 493 494 debug("DP: %s was called\n", __func__); 495 mdelay(1); 496 497 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); 498 if (ret != EXYNOS_DP_SUCCESS) { 499 printf("DP read lane status failed\n"); 500 priv->lt_info.lt_status = DP_LT_FAIL; 501 return ret; 502 } 503 504 if (lane_stat & DP_LANE_STAT_CR_DONE) { 505 debug("DP clock Recovery training succeed\n"); 506 exynos_dp_set_training_pattern(regs, TRAINING_PTN2); 507 508 for (i = 0; i < priv->lane_cnt; i++) { 509 ret = exynos_dp_read_dpcd_adj_req(regs, i, 510 &adj_req_sw, &adj_req_em); 511 if (ret != EXYNOS_DP_SUCCESS) { 512 priv->lt_info.lt_status = DP_LT_FAIL; 513 return ret; 514 } 515 516 lt_ctl_val[i] = 0; 517 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 518 519 if ((adj_req_sw == VOLTAGE_LEVEL_3) 520 || (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 521 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | 522 MAX_PRE_EMPHASIS_REACH_3; 523 } 524 exynos_dp_set_lanex_pre_emphasis(regs, 525 lt_ctl_val[i], i); 526 } 527 528 buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2; 529 buf[1] = lt_ctl_val[0]; 530 buf[2] = lt_ctl_val[1]; 531 buf[3] = lt_ctl_val[2]; 532 buf[4] = lt_ctl_val[3]; 533 534 ret = exynos_dp_write_bytes_to_dpcd(regs, 535 DPCD_TRAINING_PATTERN_SET, 5, buf); 536 if (ret != EXYNOS_DP_SUCCESS) { 537 printf("DP write training pattern1 failed\n"); 538 priv->lt_info.lt_status = DP_LT_FAIL; 539 return ret; 540 } else 541 priv->lt_info.lt_status = DP_LT_ET; 542 } else { 543 for (i = 0; i < priv->lane_cnt; i++) { 544 lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis( 545 regs, i); 546 ret = exynos_dp_read_dpcd_adj_req(regs, i, 547 &adj_req_sw, &adj_req_em); 548 if (ret != EXYNOS_DP_SUCCESS) { 549 printf("DP read adj req failed\n"); 550 priv->lt_info.lt_status = DP_LT_FAIL; 551 return ret; 552 } 553 554 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 555 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) 556 ret = exynos_dp_reduce_link_rate(regs, 557 priv); 558 559 if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) == 560 adj_req_sw) && 561 (PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) == 562 adj_req_em)) { 563 priv->lt_info.cr_loop[i]++; 564 if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP) 565 ret = exynos_dp_reduce_link_rate( 566 regs, priv); 567 } 568 569 lt_ctl_val[i] = 0; 570 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 571 572 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 573 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 574 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 | 575 MAX_PRE_EMPHASIS_REACH_3; 576 } 577 exynos_dp_set_lanex_pre_emphasis(regs, 578 lt_ctl_val[i], i); 579 } 580 581 ret = exynos_dp_write_bytes_to_dpcd(regs, 582 DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val); 583 if (ret != EXYNOS_DP_SUCCESS) { 584 printf("DP write training pattern2 failed\n"); 585 priv->lt_info.lt_status = DP_LT_FAIL; 586 return ret; 587 } 588 } 589 590 return ret; 591 } 592 593 static unsigned int exynos_dp_process_equalizer_training( 594 struct exynos_dp *regs, struct exynos_dp_priv *priv) 595 { 596 unsigned int ret; 597 unsigned char lane_stat, adj_req_sw, adj_req_em, i; 598 unsigned char lt_ctl_val[DP_LANE_CNT_4] = {0,}; 599 unsigned char interlane_aligned = 0; 600 unsigned char f_bw; 601 unsigned char f_lane_cnt; 602 unsigned char sink_stat; 603 604 mdelay(1); 605 606 ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat); 607 if (ret != EXYNOS_DP_SUCCESS) { 608 printf("DP read lane status failed\n"); 609 priv->lt_info.lt_status = DP_LT_FAIL; 610 return ret; 611 } 612 613 debug("DP lane stat : %x\n", lane_stat); 614 615 if (lane_stat & DP_LANE_STAT_CR_DONE) { 616 ret = exynos_dp_read_byte_from_dpcd(regs, 617 DPCD_LN_ALIGN_UPDATED, 618 &sink_stat); 619 if (ret != EXYNOS_DP_SUCCESS) { 620 priv->lt_info.lt_status = DP_LT_FAIL; 621 622 return ret; 623 } 624 625 interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE); 626 627 for (i = 0; i < priv->lane_cnt; i++) { 628 ret = exynos_dp_read_dpcd_adj_req(regs, i, 629 &adj_req_sw, &adj_req_em); 630 if (ret != EXYNOS_DP_SUCCESS) { 631 printf("DP read adj req 1 failed\n"); 632 priv->lt_info.lt_status = DP_LT_FAIL; 633 634 return ret; 635 } 636 637 lt_ctl_val[i] = 0; 638 lt_ctl_val[i] = adj_req_em << 3 | adj_req_sw; 639 640 if ((adj_req_sw == VOLTAGE_LEVEL_3) || 641 (adj_req_em == PRE_EMPHASIS_LEVEL_3)) { 642 lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3; 643 lt_ctl_val[i] |= MAX_PRE_EMPHASIS_REACH_3; 644 } 645 } 646 647 if (((lane_stat&DP_LANE_STAT_CE_DONE) && 648 (lane_stat&DP_LANE_STAT_SYM_LOCK)) 649 && (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) { 650 debug("DP Equalizer training succeed\n"); 651 652 f_bw = exynos_dp_get_link_bandwidth(regs); 653 f_lane_cnt = exynos_dp_get_lane_count(regs); 654 655 debug("DP final BandWidth : %x\n", f_bw); 656 debug("DP final Lane Count : %x\n", f_lane_cnt); 657 658 priv->lt_info.lt_status = DP_LT_FINISHED; 659 660 exynos_dp_equalizer_err_link(regs, priv); 661 662 } else { 663 priv->lt_info.ep_loop++; 664 665 if (priv->lt_info.ep_loop > MAX_EQ_LOOP) { 666 if (priv->lane_bw == DP_LANE_BW_2_70) { 667 ret = exynos_dp_reduce_link_rate( 668 regs, priv); 669 } else { 670 priv->lt_info.lt_status = 671 DP_LT_FAIL; 672 exynos_dp_equalizer_err_link(regs, 673 priv); 674 } 675 } else { 676 for (i = 0; i < priv->lane_cnt; i++) 677 exynos_dp_set_lanex_pre_emphasis( 678 regs, lt_ctl_val[i], i); 679 680 ret = exynos_dp_write_bytes_to_dpcd(regs, 681 DPCD_TRAINING_LANE0_SET, 682 4, lt_ctl_val); 683 if (ret != EXYNOS_DP_SUCCESS) { 684 printf("DP set lt pattern failed\n"); 685 priv->lt_info.lt_status = 686 DP_LT_FAIL; 687 exynos_dp_equalizer_err_link(regs, 688 priv); 689 } 690 } 691 } 692 } else if (priv->lane_bw == DP_LANE_BW_2_70) { 693 ret = exynos_dp_reduce_link_rate(regs, priv); 694 } else { 695 priv->lt_info.lt_status = DP_LT_FAIL; 696 exynos_dp_equalizer_err_link(regs, priv); 697 } 698 699 return ret; 700 } 701 702 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs, 703 struct exynos_dp_priv *priv) 704 { 705 unsigned int ret = 0; 706 int training_finished; 707 708 /* Turn off unnecessary lane */ 709 if (priv->lane_cnt == 1) 710 exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1); 711 712 training_finished = 0; 713 714 priv->lt_info.lt_status = DP_LT_START; 715 716 /* Process here */ 717 while (!training_finished) { 718 switch (priv->lt_info.lt_status) { 719 case DP_LT_START: 720 ret = exynos_dp_link_start(regs, priv); 721 if (ret != EXYNOS_DP_SUCCESS) { 722 printf("DP LT:link start failed\n"); 723 return ret; 724 } 725 break; 726 case DP_LT_CR: 727 ret = exynos_dp_process_clock_recovery(regs, 728 priv); 729 if (ret != EXYNOS_DP_SUCCESS) { 730 printf("DP LT:clock recovery failed\n"); 731 return ret; 732 } 733 break; 734 case DP_LT_ET: 735 ret = exynos_dp_process_equalizer_training(regs, 736 priv); 737 if (ret != EXYNOS_DP_SUCCESS) { 738 printf("DP LT:equalizer training failed\n"); 739 return ret; 740 } 741 break; 742 case DP_LT_FINISHED: 743 training_finished = 1; 744 break; 745 case DP_LT_FAIL: 746 return -1; 747 } 748 } 749 750 return ret; 751 } 752 753 static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs, 754 struct exynos_dp_priv *priv) 755 { 756 unsigned int ret; 757 758 exynos_dp_init_training(regs); 759 760 ret = exynos_dp_sw_link_training(regs, priv); 761 if (ret != EXYNOS_DP_SUCCESS) 762 printf("DP dp_sw_link_training() failed\n"); 763 764 return ret; 765 } 766 767 static void exynos_dp_enable_scramble(struct exynos_dp *regs, 768 unsigned int enable) 769 { 770 unsigned char data; 771 772 if (enable) { 773 exynos_dp_enable_scrambling(regs, DP_ENABLE); 774 775 exynos_dp_read_byte_from_dpcd(regs, 776 DPCD_TRAINING_PATTERN_SET, &data); 777 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 778 (u8)(data & ~DPCD_SCRAMBLING_DISABLED)); 779 } else { 780 exynos_dp_enable_scrambling(regs, DP_DISABLE); 781 exynos_dp_read_byte_from_dpcd(regs, 782 DPCD_TRAINING_PATTERN_SET, &data); 783 exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET, 784 (u8)(data | DPCD_SCRAMBLING_DISABLED)); 785 } 786 } 787 788 static unsigned int exynos_dp_config_video(struct exynos_dp *regs, 789 struct exynos_dp_priv *priv) 790 { 791 unsigned int ret = 0; 792 unsigned int retry_cnt; 793 794 mdelay(1); 795 796 if (priv->video_info.master_mode) { 797 printf("DP does not support master mode\n"); 798 return -ENODEV; 799 } else { 800 /* debug slave */ 801 exynos_dp_config_video_slave_mode(regs, 802 &priv->video_info); 803 } 804 805 exynos_dp_set_video_color_format(regs, &priv->video_info); 806 807 if (priv->video_info.bist_mode) { 808 if (exynos_dp_config_video_bist(regs, priv) != 0) 809 return -1; 810 } 811 812 ret = exynos_dp_get_pll_lock_status(regs); 813 if (ret != PLL_LOCKED) { 814 printf("DP PLL is not locked yet\n"); 815 return -EIO; 816 } 817 818 if (priv->video_info.master_mode == 0) { 819 retry_cnt = 10; 820 while (retry_cnt) { 821 ret = exynos_dp_is_slave_video_stream_clock_on(regs); 822 if (ret != EXYNOS_DP_SUCCESS) { 823 if (retry_cnt == 0) { 824 printf("DP stream_clock_on failed\n"); 825 return ret; 826 } 827 retry_cnt--; 828 mdelay(1); 829 } else 830 break; 831 } 832 } 833 834 /* Set to use the register calculated M/N video */ 835 exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0); 836 837 /* For video bist, Video timing must be generated by register */ 838 exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE); 839 840 /* Enable video bist */ 841 if (priv->video_info.bist_pattern != COLOR_RAMP && 842 priv->video_info.bist_pattern != BALCK_WHITE_V_LINES && 843 priv->video_info.bist_pattern != COLOR_SQUARE) 844 exynos_dp_enable_video_bist(regs, 845 priv->video_info.bist_mode); 846 else 847 exynos_dp_enable_video_bist(regs, DP_DISABLE); 848 849 /* Disable video mute */ 850 exynos_dp_enable_video_mute(regs, DP_DISABLE); 851 852 /* Configure video Master or Slave mode */ 853 exynos_dp_enable_video_master(regs, 854 priv->video_info.master_mode); 855 856 /* Enable video */ 857 exynos_dp_start_video(regs); 858 859 if (priv->video_info.master_mode == 0) { 860 retry_cnt = 100; 861 while (retry_cnt) { 862 ret = exynos_dp_is_video_stream_on(regs); 863 if (ret != EXYNOS_DP_SUCCESS) { 864 if (retry_cnt == 0) { 865 printf("DP Timeout of video stream\n"); 866 return ret; 867 } 868 retry_cnt--; 869 mdelay(5); 870 } else 871 break; 872 } 873 } 874 875 return ret; 876 } 877 878 static int exynos_dp_ofdata_to_platdata(struct udevice *dev) 879 { 880 struct exynos_dp_priv *priv = dev_get_priv(dev); 881 const void *blob = gd->fdt_blob; 882 unsigned int node = dev_of_offset(dev); 883 fdt_addr_t addr; 884 885 addr = devfdt_get_addr(dev); 886 if (addr == FDT_ADDR_T_NONE) { 887 debug("Can't get the DP base address\n"); 888 return -EINVAL; 889 } 890 priv->regs = (struct exynos_dp *)addr; 891 priv->disp_info.h_res = fdtdec_get_int(blob, node, 892 "samsung,h-res", 0); 893 priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, 894 "samsung,h-sync-width", 0); 895 priv->disp_info.h_back_porch = fdtdec_get_int(blob, node, 896 "samsung,h-back-porch", 0); 897 priv->disp_info.h_front_porch = fdtdec_get_int(blob, node, 898 "samsung,h-front-porch", 0); 899 priv->disp_info.v_res = fdtdec_get_int(blob, node, 900 "samsung,v-res", 0); 901 priv->disp_info.v_sync_width = fdtdec_get_int(blob, node, 902 "samsung,v-sync-width", 0); 903 priv->disp_info.v_back_porch = fdtdec_get_int(blob, node, 904 "samsung,v-back-porch", 0); 905 priv->disp_info.v_front_porch = fdtdec_get_int(blob, node, 906 "samsung,v-front-porch", 0); 907 priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node, 908 "samsung,v-sync-rate", 0); 909 910 priv->lt_info.lt_status = fdtdec_get_int(blob, node, 911 "samsung,lt-status", 0); 912 913 priv->video_info.master_mode = fdtdec_get_int(blob, node, 914 "samsung,master-mode", 0); 915 priv->video_info.bist_mode = fdtdec_get_int(blob, node, 916 "samsung,bist-mode", 0); 917 priv->video_info.bist_pattern = fdtdec_get_int(blob, node, 918 "samsung,bist-pattern", 0); 919 priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node, 920 "samsung,h-sync-polarity", 0); 921 priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node, 922 "samsung,v-sync-polarity", 0); 923 priv->video_info.interlaced = fdtdec_get_int(blob, node, 924 "samsung,interlaced", 0); 925 priv->video_info.color_space = fdtdec_get_int(blob, node, 926 "samsung,color-space", 0); 927 priv->video_info.dynamic_range = fdtdec_get_int(blob, node, 928 "samsung,dynamic-range", 0); 929 priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, 930 "samsung,ycbcr-coeff", 0); 931 priv->video_info.color_depth = fdtdec_get_int(blob, node, 932 "samsung,color-depth", 0); 933 return 0; 934 } 935 936 static int exynos_dp_bridge_init(struct udevice *dev) 937 { 938 const int max_tries = 10; 939 int num_tries; 940 int ret; 941 942 debug("%s\n", __func__); 943 ret = video_bridge_attach(dev); 944 if (ret) { 945 debug("video bridge init failed: %d\n", ret); 946 return ret; 947 } 948 949 /* 950 * We need to wait for 90ms after bringing up the bridge since there 951 * is a phantom "high" on the HPD chip during its bootup. The phantom 952 * high comes within 7ms of de-asserting PD and persists for at least 953 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The 954 * phantom high makes it hard for us to know when the NXP chip is up. 955 */ 956 mdelay(90); 957 958 for (num_tries = 0; num_tries < max_tries; num_tries++) { 959 /* Check HPD. If it's high, or we don't have it, all is well */ 960 ret = video_bridge_check_attached(dev); 961 if (!ret || ret == -ENOENT) 962 return 0; 963 964 debug("%s: eDP bridge failed to come up; try %d of %d\n", 965 __func__, num_tries, max_tries); 966 } 967 968 /* Immediately go into bridge reset if the hp line is not high */ 969 return -EIO; 970 } 971 972 static int exynos_dp_bridge_setup(const void *blob) 973 { 974 const int max_tries = 2; 975 int num_tries; 976 struct udevice *dev; 977 int ret; 978 979 /* Configure I2C registers for Parade bridge */ 980 ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev); 981 if (ret) { 982 debug("video bridge init failed: %d\n", ret); 983 return ret; 984 } 985 986 if (strncmp(dev->driver->name, "parade", 6)) { 987 /* Mux HPHPD to the special hotplug detect mode */ 988 exynos_pinmux_config(PERIPH_ID_DPHPD, 0); 989 } 990 991 for (num_tries = 0; num_tries < max_tries; num_tries++) { 992 ret = exynos_dp_bridge_init(dev); 993 if (!ret) 994 return 0; 995 if (num_tries == max_tries - 1) 996 break; 997 998 /* 999 * If we're here, the bridge chip failed to initialise. 1000 * Power down the bridge in an attempt to reset. 1001 */ 1002 video_bridge_set_active(dev, false); 1003 1004 /* 1005 * Arbitrarily wait 300ms here with DP_N low. Don't know for 1006 * sure how long we should wait, but we're being paranoid. 1007 */ 1008 mdelay(300); 1009 } 1010 1011 return ret; 1012 } 1013 int exynos_dp_enable(struct udevice *dev, int panel_bpp, 1014 const struct display_timing *timing) 1015 { 1016 struct exynos_dp_priv *priv = dev_get_priv(dev); 1017 struct exynos_dp *regs = priv->regs; 1018 unsigned int ret; 1019 1020 debug("%s: start\n", __func__); 1021 exynos_dp_disp_info(&priv->disp_info); 1022 1023 ret = exynos_dp_bridge_setup(gd->fdt_blob); 1024 if (ret && ret != -ENODEV) 1025 printf("LCD bridge failed to enable: %d\n", ret); 1026 1027 exynos_dp_phy_ctrl(1); 1028 1029 ret = exynos_dp_init_dp(regs); 1030 if (ret != EXYNOS_DP_SUCCESS) { 1031 printf("DP exynos_dp_init_dp() failed\n"); 1032 return ret; 1033 } 1034 1035 ret = exynos_dp_handle_edid(regs, priv); 1036 if (ret != EXYNOS_DP_SUCCESS) { 1037 printf("EDP handle_edid fail\n"); 1038 return ret; 1039 } 1040 1041 ret = exynos_dp_set_link_train(regs, priv); 1042 if (ret != EXYNOS_DP_SUCCESS) { 1043 printf("DP link training fail\n"); 1044 return ret; 1045 } 1046 1047 exynos_dp_enable_scramble(regs, DP_ENABLE); 1048 exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE); 1049 exynos_dp_enable_enhanced_mode(regs, DP_ENABLE); 1050 1051 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); 1052 exynos_dp_set_lane_count(regs, priv->lane_cnt); 1053 1054 exynos_dp_init_video(regs); 1055 ret = exynos_dp_config_video(regs, priv); 1056 if (ret != EXYNOS_DP_SUCCESS) { 1057 printf("Exynos DP init failed\n"); 1058 return ret; 1059 } 1060 1061 debug("Exynos DP init done\n"); 1062 1063 return ret; 1064 } 1065 1066 1067 static const struct dm_display_ops exynos_dp_ops = { 1068 .enable = exynos_dp_enable, 1069 }; 1070 1071 static const struct udevice_id exynos_dp_ids[] = { 1072 { .compatible = "samsung,exynos5-dp" }, 1073 { } 1074 }; 1075 1076 U_BOOT_DRIVER(exynos_dp) = { 1077 .name = "exynos_dp", 1078 .id = UCLASS_DISPLAY, 1079 .of_match = exynos_dp_ids, 1080 .ops = &exynos_dp_ops, 1081 .ofdata_to_platdata = exynos_dp_ofdata_to_platdata, 1082 .priv_auto_alloc_size = sizeof(struct exynos_dp_priv), 1083 }; 1084
