1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF54418 TWR board. 4 * 5 * Copyright 2010-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew (at) freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M54418TWR_H 14 #define _M54418TWR_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 24 25 #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 36 /* 37 * NAND FLASH 38 */ 39 #ifdef CONFIG_CMD_NAND 40 #define CONFIG_JFFS2_NAND 41 #define CONFIG_NAND_FSL_NFC 42 #define CONFIG_SYS_NAND_BASE 0xFC0FC000 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE 45 #define CONFIG_SYS_NAND_SELECT_DEVICE 46 #endif 47 48 /* Network configuration */ 49 #define CONFIG_MCFFEC 50 #ifdef CONFIG_MCFFEC 51 #define CONFIG_MII 1 52 #define CONFIG_MII_INIT 1 53 #define CONFIG_SYS_DISCOVER_PHY 54 #define CONFIG_SYS_RX_ETH_BUFFER 2 55 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 56 #define CONFIG_SYS_TX_ETH_BUFFER 2 57 #define CONFIG_HAS_ETH1 58 59 #define CONFIG_SYS_FEC0_PINMUX 0 60 #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 61 #define CONFIG_SYS_FEC1_PINMUX 0 62 #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE 63 #define MCFFEC_TOUT_LOOP 50000 64 #define CONFIG_SYS_FEC0_PHYADDR 0 65 #define CONFIG_SYS_FEC1_PHYADDR 1 66 67 #define CONFIG_ETHPRIME "FEC0" 68 #define CONFIG_IPADDR 192.168.1.2 69 #define CONFIG_NETMASK 255.255.255.0 70 #define CONFIG_SERVERIP 192.168.1.1 71 #define CONFIG_GATEWAYIP 192.168.1.1 72 73 #define CONFIG_SYS_FEC_BUF_USE_SRAM 74 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 75 #ifndef CONFIG_SYS_DISCOVER_PHY 76 #define FECDUPLEX FULL 77 #define FECSPEED _100BASET 78 #define LINKSTATUS 1 79 #else 80 #define LINKSTATUS 0 81 #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 82 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 83 #endif 84 #endif /* CONFIG_SYS_DISCOVER_PHY */ 85 #endif 86 87 #define CONFIG_HOSTNAME "M54418TWR" 88 89 #if defined(CONFIG_CF_SBF) 90 /* ST Micro serial flash */ 91 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "netdev=eth0\0" \ 94 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 95 "loadaddr=0x40010000\0" \ 96 "sbfhdr=sbfhdr.bin\0" \ 97 "uboot=u-boot.bin\0" \ 98 "load=tftp ${loadaddr} ${sbfhdr};" \ 99 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ 100 "upd=run load; run prog\0" \ 101 "prog=sf probe 0:1 1000000 3;" \ 102 "sf erase 0 40000;" \ 103 "sf write ${loadaddr} 0 40000;" \ 104 "save\0" \ 105 "" 106 #elif defined(CONFIG_SYS_NAND_BOOT) 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "netdev=eth0\0" \ 109 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 110 "loadaddr=0x40010000\0" \ 111 "u-boot=u-boot.bin\0" \ 112 "load=tftp ${loadaddr} ${u-boot};\0" \ 113 "upd=run load; run prog\0" \ 114 "prog=nand device 0;" \ 115 "nand erase 0 40000;" \ 116 "nb_update ${loadaddr} ${filesize};" \ 117 "save\0" \ 118 "" 119 #else 120 #define CONFIG_SYS_UBOOT_END 0x3FFFF 121 #define CONFIG_EXTRA_ENV_SETTINGS \ 122 "netdev=eth0\0" \ 123 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 124 "loadaddr=40010000\0" \ 125 "u-boot=u-boot.bin\0" \ 126 "load=tftp ${loadaddr) ${u-boot}\0" \ 127 "upd=run load; run prog\0" \ 128 "prog=prot off mram" " ;" \ 129 "cp.b ${loadaddr} 0 ${filesize};" \ 130 "save\0" \ 131 "" 132 #endif 133 134 /* Realtime clock */ 135 #undef CONFIG_MCFRTC 136 #define CONFIG_RTC_MCFRRTC 137 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 138 139 /* Timer */ 140 #define CONFIG_MCFTMR 141 #undef CONFIG_MCFPIT 142 143 /* I2c */ 144 #undef CONFIG_SYS_FSL_I2C 145 #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 146 /* I2C speed and slave address */ 147 #define CONFIG_SYS_I2C_SPEED 80000 148 #define CONFIG_SYS_I2C_SLAVE 0x7F 149 #define CONFIG_SYS_I2C_OFFSET 0x58000 150 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 151 152 /* DSPI and Serial Flash */ 153 #define CONFIG_CF_DSPI 154 #define CONFIG_SERIAL_FLASH 155 #define CONFIG_HARD_SPI 156 #define CONFIG_SYS_SBFHDR_SIZE 0x7 157 #ifdef CONFIG_CMD_SPI 158 159 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 160 DSPI_CTAR_PCSSCK_1CLK | \ 161 DSPI_CTAR_PASC(0) | \ 162 DSPI_CTAR_PDT(0) | \ 163 DSPI_CTAR_CSSCK(0) | \ 164 DSPI_CTAR_ASC(0) | \ 165 DSPI_CTAR_DT(1)) 166 # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 167 # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 168 #endif 169 170 /* Input, PCI, Flexbus, and VCO */ 171 #define CONFIG_EXTRA_CLOCK 172 173 #define CONFIG_PRAM 2048 /* 2048 KB */ 174 175 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 176 177 #define CONFIG_SYS_MBAR 0xFC000000 178 179 /* 180 * Low Level Configuration Settings 181 * (address mappings, register initial values, etc.) 182 * You should know what you are doing if you make changes here. 183 */ 184 185 /*----------------------------------------------------------------------- 186 * Definitions for initial stack pointer and data area (in DPRAM) 187 */ 188 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 189 /* End of used area in internal SRAM */ 190 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 191 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 192 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 193 GENERATED_GBL_DATA_SIZE) - 32) 194 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 195 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 196 197 /*----------------------------------------------------------------------- 198 * Start addresses for the final memory configuration 199 * (Set up by the startup code) 200 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 201 */ 202 #define CONFIG_SYS_SDRAM_BASE 0x40000000 203 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 204 205 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 206 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 207 #define CONFIG_SYS_DRAM_TEST 208 209 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) 210 #define CONFIG_SERIAL_BOOT 211 #endif 212 213 #if defined(CONFIG_SERIAL_BOOT) 214 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 215 #else 216 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 217 #endif 218 219 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 220 /* Reserve 256 kB for Monitor */ 221 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 222 /* Reserve 256 kB for malloc() */ 223 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 224 225 /* 226 * For booting Linux, the board info and command line data 227 * have to be in the first 8 MB of memory, since this is 228 * the maximum mapped by the Linux kernel during initialization ?? 229 */ 230 /* Initial Memory map for Linux */ 231 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 232 (CONFIG_SYS_SDRAM_SIZE << 20)) 233 234 /* Configuration for environment 235 * Environment is embedded in u-boot in the second sector of the flash 236 */ 237 #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ 238 #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ 239 #define CONFIG_ENV_SIZE 0x1000 240 #endif 241 242 #if defined(CONFIG_CF_SBF) 243 #define CONFIG_ENV_SPI_CS 1 244 #define CONFIG_ENV_OFFSET 0x40000 245 #define CONFIG_ENV_SIZE 0x2000 246 #define CONFIG_ENV_SECT_SIZE 0x10000 247 #endif 248 #if defined(CONFIG_SYS_NAND_BOOT) 249 #define CONFIG_ENV_OFFSET 0x80000 250 #define CONFIG_ENV_SIZE 0x20000 251 #define CONFIG_ENV_SECT_SIZE 0x20000 252 #endif 253 #undef CONFIG_ENV_OVERWRITE 254 255 /* FLASH organization */ 256 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 257 258 #undef CONFIG_SYS_FLASH_CFI 259 #ifdef CONFIG_SYS_FLASH_CFI 260 261 #define CONFIG_FLASH_CFI_DRIVER 1 262 /* Max size that the board might have */ 263 #define CONFIG_SYS_FLASH_SIZE 0x1000000 264 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 265 /* max number of memory banks */ 266 #define CONFIG_SYS_MAX_FLASH_BANKS 1 267 /* max number of sectors on one chip */ 268 #define CONFIG_SYS_MAX_FLASH_SECT 270 269 /* "Real" (hardware) sectors protection */ 270 #define CONFIG_SYS_FLASH_PROTECTION 271 #define CONFIG_SYS_FLASH_CHECKSUM 272 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 273 #else 274 /* max number of sectors on one chip */ 275 #define CONFIG_SYS_MAX_FLASH_SECT 270 276 /* max number of sectors on one chip */ 277 #define CONFIG_SYS_MAX_FLASH_BANKS 0 278 #endif 279 280 /* 281 * This is setting for JFFS2 support in u-boot. 282 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 283 */ 284 #ifdef CONFIG_CMD_JFFS2 285 #define CONFIG_JFFS2_DEV "nand0" 286 #define CONFIG_JFFS2_PART_OFFSET (0x800000) 287 #define CONFIG_MTD_DEVICE 288 289 #endif 290 291 #ifdef CONFIG_CMD_UBI 292 #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ 293 #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ 294 #endif 295 /* Cache Configuration */ 296 #define CONFIG_SYS_CACHELINE_SIZE 16 297 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 298 CONFIG_SYS_INIT_RAM_SIZE - 8) 299 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 300 CONFIG_SYS_INIT_RAM_SIZE - 4) 301 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 302 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 303 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 304 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 305 CF_ACR_EN | CF_ACR_SM_ALL) 306 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 307 CF_CACR_ICINVA | CF_CACR_EUSP) 308 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 309 CF_CACR_DEC | CF_CACR_DDCM_P | \ 310 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 311 312 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 313 CONFIG_SYS_INIT_RAM_SIZE - 12) 314 315 /*----------------------------------------------------------------------- 316 * Memory bank definitions 317 */ 318 /* 319 * CS0 - NOR Flash 16MB 320 * CS1 - Available 321 * CS2 - Available 322 * CS3 - Available 323 * CS4 - Available 324 * CS5 - Available 325 */ 326 327 /* Flash */ 328 #define CONFIG_SYS_CS0_BASE 0x00000000 329 #define CONFIG_SYS_CS0_MASK 0x000F0101 330 #define CONFIG_SYS_CS0_CTRL 0x00001D60 331 332 #endif /* _M54418TWR_H */ 333
