1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. 4 */ 5 6 /* 7 * mpc8548cds board configuration file 8 * 9 * Please refer to doc/README.mpc85xxcds for more info. 10 * 11 */ 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_SYS_SRIO 16 #define CONFIG_SRIO1 /* SRIO port 1 */ 17 18 #define CONFIG_PCI1 /* PCI controller 1 */ 19 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 20 #undef CONFIG_PCI2 21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 23 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 25 26 #define CONFIG_ENV_OVERWRITE 27 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 28 29 #define CONFIG_FSL_VIA 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_clock_freq(void); 33 #endif 34 #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 /* 43 * Only possible on E500 Version 2 or newer cores. 44 */ 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #ifdef CONFIG_PHYS_64BIT 48 #define CONFIG_ADDR_MAP 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x00400000 54 55 #define CONFIG_SYS_CCSRBAR 0xe0000000 56 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 57 58 /* DDR Setup */ 59 #undef CONFIG_FSL_DDR_INTERACTIVE 60 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 61 #define CONFIG_DDR_SPD 62 63 #define CONFIG_DDR_ECC 64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 65 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 66 67 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 68 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 69 70 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 71 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 72 73 /* I2C addresses of SPD EEPROMs */ 74 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 75 76 /* Make sure required options are set */ 77 #ifndef CONFIG_SPD_EEPROM 78 #error ("CONFIG_SPD_EEPROM is required") 79 #endif 80 81 #undef CONFIG_CLOCKS_IN_MHZ 82 /* 83 * Physical Address Map 84 * 85 * 32bit: 86 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable 87 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable 88 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable 89 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable 90 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable 91 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable 92 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable 93 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable 94 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable 95 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable 96 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable 97 * 98 * 36bit: 99 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable 100 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable 101 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable 102 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable 103 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable 104 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable 105 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable 106 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable 107 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable 108 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable 109 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable 110 * 111 */ 112 113 /* 114 * Local Bus Definitions 115 */ 116 117 /* 118 * FLASH on the Local Bus 119 * Two banks, 8M each, using the CFI driver. 120 * Boot from BR0/OR0 bank at 0xff00_0000 121 * Alternate BR1/OR1 bank at 0xff80_0000 122 * 123 * BR0, BR1: 124 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 125 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 126 * Port Size = 16 bits = BRx[19:20] = 10 127 * Use GPCM = BRx[24:26] = 000 128 * Valid = BRx[31] = 1 129 * 130 * 0 4 8 12 16 20 24 28 131 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 132 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 133 * 134 * OR0, OR1: 135 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 136 * Reserved ORx[17:18] = 11, confusion here? 137 * CSNT = ORx[20] = 1 138 * ACS = half cycle delay = ORx[21:22] = 11 139 * SCY = 6 = ORx[24:27] = 0110 140 * TRLX = use relaxed timing = ORx[29] = 1 141 * EAD = use external address latch delay = OR[31] = 1 142 * 143 * 0 4 8 12 16 20 24 28 144 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx 145 */ 146 147 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull 150 #else 151 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 152 #endif 153 154 #define CONFIG_SYS_BR0_PRELIM \ 155 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) 156 #define CONFIG_SYS_BR1_PRELIM \ 157 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 158 159 #define CONFIG_SYS_OR0_PRELIM 0xff806e65 160 #define CONFIG_SYS_OR1_PRELIM 0xff806e65 161 162 #define CONFIG_SYS_FLASH_BANKS_LIST \ 163 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} 164 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 165 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ 166 #undef CONFIG_SYS_FLASH_CHECKSUM 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 171 172 #define CONFIG_FLASH_CFI_DRIVER 173 #define CONFIG_SYS_FLASH_CFI 174 #define CONFIG_SYS_FLASH_EMPTY_INFO 175 176 #define CONFIG_HWCONFIG /* enable hwconfig */ 177 178 /* 179 * SDRAM on the Local Bus 180 */ 181 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull 184 #else 185 #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE 186 #endif 187 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 188 189 /* 190 * Base Register 2 and Option Register 2 configure SDRAM. 191 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 192 * 193 * For BR2, need: 194 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 195 * port-size = 32-bits = BR2[19:20] = 11 196 * no parity checking = BR2[21:22] = 00 197 * SDRAM for MSEL = BR2[24:26] = 011 198 * Valid = BR[31] = 1 199 * 200 * 0 4 8 12 16 20 24 28 201 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 202 * 203 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 204 * FIXME: the top 17 bits of BR2. 205 */ 206 207 #define CONFIG_SYS_BR2_PRELIM \ 208 (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ 209 | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) 210 211 /* 212 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 213 * 214 * For OR2, need: 215 * 64MB mask for AM, OR2[0:7] = 1111 1100 216 * XAM, OR2[17:18] = 11 217 * 9 columns OR2[19-21] = 010 218 * 13 rows OR2[23-25] = 100 219 * EAD set for extra time OR[31] = 1 220 * 221 * 0 4 8 12 16 20 24 28 222 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 223 */ 224 225 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 226 227 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 228 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 229 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 230 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 231 232 /* 233 * Common settings for all Local Bus SDRAM commands. 234 * At run time, either BSMA1516 (for CPU 1.1) 235 * or BSMA1617 (for CPU 1.0) (old) 236 * is OR'ed in too. 237 */ 238 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ 239 | LSDMR_PRETOACT7 \ 240 | LSDMR_ACTTORW7 \ 241 | LSDMR_BL8 \ 242 | LSDMR_WRC4 \ 243 | LSDMR_CL3 \ 244 | LSDMR_RFEN \ 245 ) 246 247 /* 248 * The CADMUS registers are connected to CS3 on CDS. 249 * The new memory map places CADMUS at 0xf8000000. 250 * 251 * For BR3, need: 252 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 253 * port-size = 8-bits = BR[19:20] = 01 254 * no parity checking = BR[21:22] = 00 255 * GPMC for MSEL = BR[24:26] = 000 256 * Valid = BR[31] = 1 257 * 258 * 0 4 8 12 16 20 24 28 259 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 260 * 261 * For OR3, need: 262 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 263 * disable buffer ctrl OR[19] = 0 264 * CSNT OR[20] = 1 265 * ACS OR[21:22] = 11 266 * XACS OR[23] = 1 267 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe 268 * SETA OR[28] = 0 269 * TRLX OR[29] = 1 270 * EHTR OR[30] = 1 271 * EAD extra time OR[31] = 1 272 * 273 * 0 4 8 12 16 20 24 28 274 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 275 */ 276 277 #define CONFIG_FSL_CADMUS 278 279 #define CADMUS_BASE_ADDR 0xf8000000 280 #ifdef CONFIG_PHYS_64BIT 281 #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull 282 #else 283 #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR 284 #endif 285 #define CONFIG_SYS_BR3_PRELIM \ 286 (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) 287 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 288 289 #define CONFIG_SYS_INIT_RAM_LOCK 1 290 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 291 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 292 293 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 294 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 295 296 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 297 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 298 299 /* Serial Port */ 300 #define CONFIG_SYS_NS16550_SERIAL 301 #define CONFIG_SYS_NS16550_REG_SIZE 1 302 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 303 304 #define CONFIG_SYS_BAUDRATE_TABLE \ 305 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 306 307 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 308 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 309 310 /* 311 * I2C 312 */ 313 #define CONFIG_SYS_I2C 314 #define CONFIG_SYS_I2C_FSL 315 #define CONFIG_SYS_FSL_I2C_SPEED 400000 316 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 317 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 318 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 319 320 /* EEPROM */ 321 #define CONFIG_ID_EEPROM 322 #define CONFIG_SYS_I2C_EEPROM_CCID 323 #define CONFIG_SYS_ID_EEPROM 324 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 326 327 /* 328 * General PCI 329 * Memory space is mapped 1-1, but I/O space must start from 0. 330 */ 331 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 332 #ifdef CONFIG_PHYS_64BIT 333 #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 334 #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull 335 #else 336 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 337 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 338 #endif 339 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 340 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 341 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 342 #ifdef CONFIG_PHYS_64BIT 343 #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull 344 #else 345 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 346 #endif 347 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 348 349 #ifdef CONFIG_PCIE1 350 #define CONFIG_SYS_PCIE1_NAME "Slot" 351 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 352 #ifdef CONFIG_PHYS_64BIT 353 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull 355 #else 356 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 357 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 358 #endif 359 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 360 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 361 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 362 #ifdef CONFIG_PHYS_64BIT 363 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull 364 #else 365 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 366 #endif 367 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 368 #endif 369 370 /* 371 * RapidIO MMU 372 */ 373 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 374 #ifdef CONFIG_PHYS_64BIT 375 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull 376 #else 377 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 378 #endif 379 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 380 381 #ifdef CONFIG_LEGACY 382 #define BRIDGE_ID 17 383 #define VIA_ID 2 384 #else 385 #define BRIDGE_ID 28 386 #define VIA_ID 4 387 #endif 388 389 #if defined(CONFIG_PCI) 390 #undef CONFIG_EEPRO100 391 #undef CONFIG_TULIP 392 393 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 394 395 #endif /* CONFIG_PCI */ 396 397 #if defined(CONFIG_TSEC_ENET) 398 399 #define CONFIG_MII 1 /* MII PHY management */ 400 #define CONFIG_TSEC1 1 401 #define CONFIG_TSEC1_NAME "eTSEC0" 402 #define CONFIG_TSEC2 1 403 #define CONFIG_TSEC2_NAME "eTSEC1" 404 #define CONFIG_TSEC3 1 405 #define CONFIG_TSEC3_NAME "eTSEC2" 406 #define CONFIG_TSEC4 407 #define CONFIG_TSEC4_NAME "eTSEC3" 408 #undef CONFIG_MPC85XX_FEC 409 410 #define TSEC1_PHY_ADDR 0 411 #define TSEC2_PHY_ADDR 1 412 #define TSEC3_PHY_ADDR 2 413 #define TSEC4_PHY_ADDR 3 414 415 #define TSEC1_PHYIDX 0 416 #define TSEC2_PHYIDX 0 417 #define TSEC3_PHYIDX 0 418 #define TSEC4_PHYIDX 0 419 #define TSEC1_FLAGS TSEC_GIGABIT 420 #define TSEC2_FLAGS TSEC_GIGABIT 421 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 422 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 424 /* Options are: eTSEC[0-3] */ 425 #define CONFIG_ETHPRIME "eTSEC0" 426 #endif /* CONFIG_TSEC_ENET */ 427 428 /* 429 * Environment 430 */ 431 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 432 #define CONFIG_ENV_ADDR 0xfff80000 433 #else 434 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 435 #endif 436 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ 437 #define CONFIG_ENV_SIZE 0x2000 438 439 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 440 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 441 442 /* 443 * BOOTP options 444 */ 445 #define CONFIG_BOOTP_BOOTFILESIZE 446 447 #undef CONFIG_WATCHDOG /* watchdog disabled */ 448 449 /* 450 * Miscellaneous configurable options 451 */ 452 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 453 454 /* 455 * For booting Linux, the board info and command line data 456 * have to be in the first 64 MB of memory, since this is 457 * the maximum mapped by the Linux kernel during initialization. 458 */ 459 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 460 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 461 462 #if defined(CONFIG_CMD_KGDB) 463 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 464 #endif 465 466 /* 467 * Environment Configuration 468 */ 469 #if defined(CONFIG_TSEC_ENET) 470 #define CONFIG_HAS_ETH0 471 #define CONFIG_HAS_ETH1 472 #define CONFIG_HAS_ETH2 473 #define CONFIG_HAS_ETH3 474 #endif 475 476 #define CONFIG_IPADDR 192.168.1.253 477 478 #define CONFIG_HOSTNAME "unknown" 479 #define CONFIG_ROOTPATH "/nfsroot" 480 #define CONFIG_BOOTFILE "8548cds/uImage.uboot" 481 #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ 482 483 #define CONFIG_SERVERIP 192.168.1.1 484 #define CONFIG_GATEWAYIP 192.168.1.1 485 #define CONFIG_NETMASK 255.255.255.0 486 487 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ 488 489 #define CONFIG_EXTRA_ENV_SETTINGS \ 490 "hwconfig=fsl_ddr:ecc=off\0" \ 491 "netdev=eth0\0" \ 492 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 493 "tftpflash=tftpboot $loadaddr $uboot; " \ 494 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 495 " +$filesize; " \ 496 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 497 " +$filesize; " \ 498 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 499 " $filesize; " \ 500 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 501 " +$filesize; " \ 502 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 503 " $filesize\0" \ 504 "consoledev=ttyS1\0" \ 505 "ramdiskaddr=2000000\0" \ 506 "ramdiskfile=ramdisk.uboot\0" \ 507 "fdtaddr=1e00000\0" \ 508 "fdtfile=mpc8548cds.dtb\0" 509 510 #define CONFIG_NFSBOOTCOMMAND \ 511 "setenv bootargs root=/dev/nfs rw " \ 512 "nfsroot=$serverip:$rootpath " \ 513 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 514 "console=$consoledev,$baudrate $othbootargs;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "tftp $fdtaddr $fdtfile;" \ 517 "bootm $loadaddr - $fdtaddr" 518 519 #define CONFIG_RAMBOOTCOMMAND \ 520 "setenv bootargs root=/dev/ram rw " \ 521 "console=$consoledev,$baudrate $othbootargs;" \ 522 "tftp $ramdiskaddr $ramdiskfile;" \ 523 "tftp $loadaddr $bootfile;" \ 524 "tftp $fdtaddr $fdtfile;" \ 525 "bootm $loadaddr $ramdiskaddr $fdtaddr" 526 527 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 528 529 #endif /* __CONFIG_H */ 530
