1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 Ilya Yanok, Emcraft Systems 4 * 5 * Based on omap3_evm_config.h 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 /* 12 * High Level Configuration Options 13 */ 14 15 #define CONFIG_MACH_TYPE MACH_TYPE_MCX 16 17 #include <asm/arch/cpu.h> /* get chip and board defs */ 18 #include <asm/arch/omap.h> 19 20 /* 21 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader 22 * and older u-boot.bin with the new U-Boot SPL. 23 */ 24 25 /* Clock Defines */ 26 #define V_OSCK 26000000 /* Clock output from T2 */ 27 #define V_SCLK (V_OSCK >> 1) 28 29 #define CONFIG_MISC_INIT_R 30 31 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 32 #define CONFIG_SETUP_MEMORY_TAGS 33 #define CONFIG_INITRD_TAG 34 #define CONFIG_REVISION_TAG 35 36 /* 37 * Size of malloc() pool 38 */ 39 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 40 #define CONFIG_SYS_MALLOC_LEN (1024 << 10) 41 /* 42 * DDR related 43 */ 44 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 45 46 /* 47 * Hardware drivers 48 */ 49 50 /* 51 * NS16550 Configuration 52 */ 53 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 54 55 #define CONFIG_SYS_NS16550_SERIAL 56 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 57 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 58 59 /* 60 * select serial console configuration 61 */ 62 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 63 #define CONFIG_SERIAL3 3 /* UART3 */ 64 65 /* allow to overwrite serial and ethaddr */ 66 #define CONFIG_ENV_OVERWRITE 67 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 68 115200} 69 70 /* EHCI */ 71 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 72 73 /* commands to include */ 74 75 #define CONFIG_MTD_PARTITIONS 76 #define CONFIG_MTD_DEVICE 77 78 #define CONFIG_SYS_I2C 79 80 /* RTC */ 81 #define CONFIG_RTC_DS1337 82 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 83 84 /* 85 * Board NAND Info. 86 */ 87 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 88 /* to access nand */ 89 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 90 /* to access */ 91 /* nand at CS0 */ 92 93 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 94 /* NAND devices */ 95 #define CONFIG_JFFS2_NAND 96 /* nand device jffs2 lives on */ 97 #define CONFIG_JFFS2_DEV "nand0" 98 /* start of jffs2 partition */ 99 #define CONFIG_JFFS2_PART_OFFSET 0x680000 100 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 101 102 /* Environment information */ 103 104 #define CONFIG_BOOTFILE "uImage" 105 106 /* Setup MTD for NAND on the SOM */ 107 108 #define CONFIG_HOSTNAME "mcx" 109 #define CONFIG_EXTRA_ENV_SETTINGS \ 110 "adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0" \ 111 "adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0" \ 112 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ 113 "addfb=setenv bootargs ${bootargs} vram=6M " \ 114 "omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0" \ 115 "addip_sta=setenv bootargs ${bootargs} " \ 116 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 117 "${netmask}:${hostname}:eth0:off\0" \ 118 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 119 "addip=if test -n ${ipdyn};then run addip_dyn;" \ 120 "else run addip_sta;fi\0" \ 121 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 122 "addtty=setenv bootargs ${bootargs} " \ 123 "console=${consoledev},${baudrate}\0" \ 124 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 125 "baudrate=115200\0" \ 126 "consoledev=ttyO2\0" \ 127 "hostname=" CONFIG_HOSTNAME "\0" \ 128 "loadaddr=0x82000000\0" \ 129 "load=tftp ${loadaddr} ${u-boot}\0" \ 130 "load_k=tftp ${loadaddr} ${bootfile}\0" \ 131 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 132 "loadmlo=tftp ${loadaddr} ${mlo}\0" \ 133 "mlo=" CONFIG_HOSTNAME "/MLO\0" \ 134 "mmcargs=root=/dev/mmcblk0p2 rw " \ 135 "rootfstype=ext3 rootwait\0" \ 136 "mmcboot=echo Booting from mmc ...; " \ 137 "run mmcargs; " \ 138 "run addip addtty addmtd addfb addeth addmisc;" \ 139 "run loaduimage; " \ 140 "bootm ${loadaddr}\0" \ 141 "net_nfs=run load_k; " \ 142 "run nfsargs; " \ 143 "run addip addtty addmtd addfb addeth addmisc;" \ 144 "bootm ${loadaddr}\0" \ 145 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 146 "nfsroot=${serverip}:${rootpath}\0" \ 147 "u-boot=" CONFIG_HOSTNAME "/u-boot.img\0" \ 148 "uboot_addr=0x80000\0" \ 149 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \ 150 "nand write ${loadaddr} ${uboot_addr} 80000\0" \ 151 "updatemlo=nandecc hw;nand erase 0 20000;" \ 152 "nand write ${loadaddr} 0 20000\0" \ 153 "upd=if run load;then echo Updating u-boot;if run update;" \ 154 "then echo U-Boot updated;" \ 155 "else echo Error updating u-boot !;" \ 156 "echo Board without bootloader !!;" \ 157 "fi;" \ 158 "else echo U-Boot not downloaded..exiting;fi\0" \ 159 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 160 "bootscript=echo Running bootscript from mmc ...; " \ 161 "source ${loadaddr}\0" \ 162 "nandargs=setenv bootargs ubi.mtd=7 " \ 163 "root=ubi0:rootfs rootfstype=ubifs\0" \ 164 "nandboot=echo Booting from nand ...; " \ 165 "run nandargs; " \ 166 "ubi part nand0,4;" \ 167 "ubi readvol ${loadaddr} kernel;" \ 168 "run addtty addmtd addfb addeth addmisc;" \ 169 "bootm ${loadaddr}\0" \ 170 "preboot=ubi part nand0,7;" \ 171 "ubi readvol ${loadaddr} splash;" \ 172 "bmp display ${loadaddr};" \ 173 "gpio set 55\0" \ 174 "swupdate_args=setenv bootargs root=/dev/ram " \ 175 "quiet loglevel=1 " \ 176 "consoleblank=0 ${swupdate_misc}\0" \ 177 "swupdate=echo Running Sw-Update...;" \ 178 "if printenv mtdparts;then echo Starting SwUpdate...; " \ 179 "else mtdparts default;fi; " \ 180 "ubi part nand0,5;" \ 181 "ubi readvol 0x82000000 kernel_recovery;" \ 182 "ubi part nand0,6;" \ 183 "ubi readvol 0x84000000 fs_recovery;" \ 184 "run swupdate_args; " \ 185 "setenv bootargs ${bootargs} " \ 186 "${mtdparts} " \ 187 "vram=6M omapfb.vram=1:2M,2:2M,3:2M " \ 188 "omapdss.def_disp=lcd;" \ 189 "bootm 0x82000000 0x84000000\0" \ 190 "bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \ 191 "then source 82000000;else run nandboot;fi\0" 192 193 /* 194 * Miscellaneous configurable options 195 */ 196 #define CONFIG_SYS_CBSIZE 1024/* Console I/O Buffer Size */ 197 /* Boot Argument Buffer Size */ 198 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 199 /* memtest works on */ 200 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 201 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 202 0x01F00000) /* 31MB */ 203 204 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 205 /* address */ 206 #define CONFIG_PREBOOT 207 208 /* 209 * AM3517 has 12 GP timers, they can be driven by the system clock 210 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 211 * This rate is divided by a local divisor. 212 */ 213 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 214 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 215 216 /* 217 * Physical Memory Map 218 */ 219 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 220 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 221 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 222 223 /* 224 * FLASH and environment organization 225 */ 226 227 /* **** PISMO SUPPORT *** */ 228 229 /* Redundant Environment */ 230 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 231 #define CONFIG_ENV_OFFSET 0x180000 232 #define CONFIG_ENV_ADDR 0x180000 233 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 234 2 * CONFIG_SYS_ENV_SECT_SIZE) 235 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 236 237 /* Flash banks JFFS2 should use */ 238 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 239 CONFIG_SYS_MAX_NAND_DEVICE) 240 #define CONFIG_SYS_JFFS2_MEM_NAND 241 /* use flash_info[2] */ 242 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 243 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 244 245 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 246 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 247 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 248 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 249 CONFIG_SYS_INIT_RAM_SIZE - \ 250 GENERATED_GBL_DATA_SIZE) 251 252 /* Defines for SPL */ 253 254 #define CONFIG_SPL_NAND_BASE 255 #define CONFIG_SPL_NAND_DRIVERS 256 #define CONFIG_SPL_NAND_ECC 257 258 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 259 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ 260 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 261 262 /* move malloc and bss high to prevent clashing with the main image */ 263 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 264 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 265 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ 266 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 267 268 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 269 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 270 271 /* NAND boot config */ 272 #define CONFIG_SYS_NAND_PAGE_COUNT 64 273 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 274 #define CONFIG_SYS_NAND_OOBSIZE 64 275 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 276 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 277 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 278 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ 279 48, 49, 50, 51, 52, 53, 54, 55,\ 280 56, 57, 58, 59, 60, 61, 62, 63} 281 #define CONFIG_SYS_NAND_ECCSIZE 256 282 #define CONFIG_SYS_NAND_ECCBYTES 3 283 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW 284 #define CONFIG_SPL_NAND_SOFTECC 285 286 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 287 288 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 289 290 /* 291 * ethernet support 292 * 293 */ 294 #if defined(CONFIG_CMD_NET) 295 #define CONFIG_DRIVER_TI_EMAC 296 #define CONFIG_DRIVER_TI_EMAC_USE_RMII 297 #define CONFIG_MII 298 #define CONFIG_BOOTP_DNS2 299 #define CONFIG_BOOTP_SEND_HOSTNAME 300 #define CONFIG_NET_RETRY_COUNT 10 301 #endif 302 303 #define CONFIG_SPLASH_SCREEN 304 #define CONFIG_VIDEO_BMP_RLE8 305 #define CONFIG_VIDEO_OMAP3 306 307 #endif /* __CONFIG_H */ 308
