1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * 5 * Configuration settings for the Freescale i.MX6SX Sabreauto board. 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include "mx6_common.h" 12 13 /* Size of malloc() pool */ 14 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) 15 16 #define CONFIG_MXC_UART 17 #define CONFIG_MXC_UART_BASE UART1_BASE 18 19 #define CONFIG_EXTRA_ENV_SETTINGS \ 20 "script=boot.scr\0" \ 21 "image=zImage\0" \ 22 "console=ttymxc0\0" \ 23 "fdt_high=0xffffffff\0" \ 24 "initrd_high=0xffffffff\0" \ 25 "fdt_file=imx6sx-sabreauto.dtb\0" \ 26 "fdt_addr=0x88000000\0" \ 27 "boot_fdt=try\0" \ 28 "ip_dyn=yes\0" \ 29 "mmcdev=0\0" \ 30 "mmcpart=1\0" \ 31 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ 32 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 33 "root=${mmcroot}\0" \ 34 "loadbootscript=" \ 35 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 36 "bootscript=echo Running bootscript from mmc ...; " \ 37 "source\0" \ 38 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 39 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ 40 "mmcboot=echo Booting from mmc ...; " \ 41 "run mmcargs; " \ 42 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 43 "if run loadfdt; then " \ 44 "bootz ${loadaddr} - ${fdt_addr}; " \ 45 "else " \ 46 "if test ${boot_fdt} = try; then " \ 47 "bootz; " \ 48 "else " \ 49 "echo WARN: Cannot load the DT; " \ 50 "fi; " \ 51 "fi; " \ 52 "else " \ 53 "bootz; " \ 54 "fi;\0" \ 55 "netargs=setenv bootargs console=${console},${baudrate} " \ 56 "root=/dev/nfs " \ 57 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 58 "netboot=echo Booting from net ...; " \ 59 "run netargs; " \ 60 "if test ${ip_dyn} = yes; then " \ 61 "setenv get_cmd dhcp; " \ 62 "else " \ 63 "setenv get_cmd tftp; " \ 64 "fi; " \ 65 "${get_cmd} ${image}; " \ 66 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 67 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ 68 "bootz ${loadaddr} - ${fdt_addr}; " \ 69 "else " \ 70 "if test ${boot_fdt} = try; then " \ 71 "bootz; " \ 72 "else " \ 73 "echo WARN: Cannot load the DT; " \ 74 "fi; " \ 75 "fi; " \ 76 "else " \ 77 "bootz; " \ 78 "fi;\0" 79 80 #define CONFIG_BOOTCOMMAND \ 81 "mmc dev ${mmcdev};" \ 82 "mmc dev ${mmcdev}; if mmc rescan; then " \ 83 "if run loadbootscript; then " \ 84 "run bootscript; " \ 85 "else " \ 86 "if run loadimage; then " \ 87 "run mmcboot; " \ 88 "else run netboot; " \ 89 "fi; " \ 90 "fi; " \ 91 "else run netboot; fi" 92 93 /* Miscellaneous configurable options */ 94 #define CONFIG_SYS_MEMTEST_START 0x80000000 95 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) 96 97 /* Physical Memory Map */ 98 #define CONFIG_NR_DRAM_BANKS 1 99 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 100 101 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 102 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 103 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 104 105 #define CONFIG_SYS_INIT_SP_OFFSET \ 106 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 107 #define CONFIG_SYS_INIT_SP_ADDR \ 108 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 109 110 /* MMC Configuration */ 111 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR 112 113 /* I2C Configs */ 114 #define CONFIG_SYS_I2C_MXC 115 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 116 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 117 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 118 #define CONFIG_SYS_I2C_SPEED 100000 119 120 /* NAND stuff */ 121 #define CONFIG_SYS_MAX_NAND_DEVICE 1 122 #define CONFIG_SYS_NAND_BASE 0x40000000 123 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 124 #define CONFIG_SYS_NAND_ONFI_DETECTION 125 126 /* DMA stuff, needed for GPMI/MXS NAND support */ 127 128 /* Network */ 129 130 #define CONFIG_FEC_MXC 131 #define CONFIG_MII 132 133 #define IMX_FEC_BASE ENET2_BASE_ADDR 134 #define CONFIG_FEC_MXC_PHYADDR 0x0 135 136 #define CONFIG_FEC_XCV_TYPE RGMII 137 #define CONFIG_ETHPRIME "FEC" 138 139 #define CONFIG_PHY_ATHEROS 140 141 #ifdef CONFIG_CMD_USB 142 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 143 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 144 #define CONFIG_MXC_USB_FLAGS 0 145 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 146 #endif 147 148 #define CONFIG_IMX_THERMAL 149 150 #ifdef CONFIG_FSL_QSPI 151 #define CONFIG_SYS_FSL_QSPI_AHB 152 #define CONFIG_SF_DEFAULT_BUS 0 153 #define CONFIG_SF_DEFAULT_CS 0 154 #define CONFIG_SF_DEFAULT_SPEED 40000000 155 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 156 #define FSL_QSPI_FLASH_SIZE SZ_32M 157 #define FSL_QSPI_FLASH_NUM 2 158 #endif 159 160 #define CONFIG_ENV_OFFSET (8 * SZ_64K) 161 #define CONFIG_ENV_SIZE SZ_8K 162 163 #define CONFIG_SYS_FSL_USDHC_NUM 2 164 #if defined(CONFIG_ENV_IS_IN_MMC) 165 #define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ 166 #endif 167 168 #endif /* __CONFIG_H */ 169
