1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuration settings for the SAMA5D4 Xplained ultra board. 4 * 5 * Copyright (C) 2014 Atmel 6 * Bo Shen <voice.shen (at) atmel.com> 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include "at91-sama5_common.h" 13 14 #define CONFIG_MISC_INIT_R 15 16 /* SDRAM */ 17 #define CONFIG_NR_DRAM_BANKS 1 18 #define CONFIG_SYS_SDRAM_BASE 0x20000000 19 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 20 21 #ifdef CONFIG_SPL_BUILD 22 #define CONFIG_SYS_INIT_SP_ADDR 0x218000 23 #else 24 #define CONFIG_SYS_INIT_SP_ADDR \ 25 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 26 #endif 27 28 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 29 30 #ifdef CONFIG_CMD_SF 31 #define CONFIG_SF_DEFAULT_SPEED 30000000 32 #endif 33 34 /* NAND flash */ 35 #ifdef CONFIG_CMD_NAND 36 #define CONFIG_NAND_ATMEL 37 #define CONFIG_SYS_MAX_NAND_DEVICE 1 38 #define CONFIG_SYS_NAND_BASE 0x80000000 39 /* our ALE is AD21 */ 40 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 41 /* our CLE is AD22 */ 42 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 43 #define CONFIG_SYS_NAND_ONFI_DETECTION 44 /* PMECC & PMERRLOC */ 45 #define CONFIG_ATMEL_NAND_HWECC 46 #define CONFIG_ATMEL_NAND_HW_PMECC 47 #endif 48 49 /* SPL */ 50 #define CONFIG_SPL_TEXT_BASE 0x200000 51 #define CONFIG_SPL_MAX_SIZE 0x18000 52 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 53 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 54 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 55 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 56 57 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 58 59 #ifdef CONFIG_SD_BOOT 60 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 61 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 62 63 #elif CONFIG_SYS_USE_NANDFLASH 64 #elif CONFIG_SPI_BOOT 65 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x10000 66 67 #elif CONFIG_NAND_BOOT 68 #define CONFIG_SPL_NAND_DRIVERS 69 #define CONFIG_SPL_NAND_BASE 70 #endif 71 #define CONFIG_PMECC_CAP 8 72 #define CONFIG_PMECC_SECTOR_SIZE 512 73 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 74 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 75 #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 76 #define CONFIG_SYS_NAND_PAGE_COUNT 64 77 #define CONFIG_SYS_NAND_OOBSIZE 224 78 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 79 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 80 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 81 82 #endif 83
