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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * Copyright (C) 2011 Samsung Electronics
      4  *
      5  * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
      6  */
      7 
      8 #ifndef __CONFIG_H
      9 #define __CONFIG_H
     10 
     11 #include "exynos4-common.h"
     12 
     13 #undef CONFIG_BOARD_COMMON
     14 #undef CONFIG_USB_GADGET_DWC2_OTG_PHY
     15 #undef CONFIG_REVISION_TAG
     16 
     17 /* High Level Configuration Options */
     18 #define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
     19 
     20 /* Mach Type */
     21 #define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
     22 
     23 #define CONFIG_SYS_SDRAM_BASE		0x40000000
     24 
     25 /* Handling Sleep Mode*/
     26 #define S5P_CHECK_SLEEP			0x00000BAD
     27 #define S5P_CHECK_DIDLE			0xBAD00000
     28 #define S5P_CHECK_LPA			0xABAD0000
     29 
     30 /* select serial console configuration */
     31 #define CONFIG_SERIAL1			1	/* use SERIAL 1 */
     32 #define EXYNOS4_DEFAULT_UART_OFFSET	0x010000
     33 
     34 /* allow to overwrite serial and ethaddr */
     35 #define CONFIG_ENV_OVERWRITE
     36 
     37 /* MMC SPL */
     38 #define CONFIG_SKIP_LOWLEVEL_INIT
     39 #define COPY_BL2_FNPTR_ADDR	0x00002488
     40 
     41 #define CONFIG_SPL_TEXT_BASE	0x02021410
     42 
     43 #define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
     44 
     45 /* Miscellaneous configurable options */
     46 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
     47 /* memtest works on */
     48 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
     49 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
     50 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
     51 
     52 /* SMDKV310 has 4 bank of DRAM */
     53 #define CONFIG_NR_DRAM_BANKS	4
     54 #define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
     55 #define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
     56 #define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
     57 #define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
     58 #define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
     59 #define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
     60 #define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
     61 #define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
     62 #define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
     63 
     64 /* FLASH and environment organization */
     65 
     66 #define CONFIG_CLK_1000_400_200
     67 
     68 /* MIU (Memory Interleaving Unit) */
     69 #define CONFIG_MIU_2BIT_INTERLEAVED
     70 
     71 #define CONFIG_SYS_MMC_ENV_DEV		0
     72 #define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
     73 #define RESERVE_BLOCK_SIZE		(512)
     74 #define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
     75 #define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
     76 
     77 #define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
     78 
     79 #define CONFIG_SYS_INIT_SP_ADDR		0x02040000
     80 
     81 /* U-Boot copy size from boot Media to DRAM.*/
     82 #define	COPY_BL2_SIZE		0x80000
     83 #define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
     84 #define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
     85 
     86 /* Ethernet Controllor Driver */
     87 #ifdef CONFIG_CMD_NET
     88 #define CONFIG_ENV_SROM_BANK		1
     89 #endif /*CONFIG_CMD_NET*/
     90 
     91 #endif	/* __CONFIG_H */
     92