1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton (at) mips.com> 5 */ 6 7 #ifndef __MSC01_H__ 8 #define __MSC01_H__ 9 10 /* 11 * Bus Interface Unit 12 */ 13 14 #define MSC01_BIU_IP1BAS1L_OFS 0x0208 15 #define MSC01_BIU_IP1MSK1L_OFS 0x0218 16 #define MSC01_BIU_IP1BAS2L_OFS 0x0248 17 #define MSC01_BIU_IP1MSK2L_OFS 0x0258 18 #define MSC01_BIU_IP2BAS1L_OFS 0x0288 19 #define MSC01_BIU_IP2MSK1L_OFS 0x0298 20 #define MSC01_BIU_IP2BAS2L_OFS 0x02c8 21 #define MSC01_BIU_IP2MSK2L_OFS 0x02d8 22 #define MSC01_BIU_IP3BAS1L_OFS 0x0308 23 #define MSC01_BIU_IP3MSK1L_OFS 0x0318 24 #define MSC01_BIU_IP3BAS2L_OFS 0x0348 25 #define MSC01_BIU_IP3MSK2L_OFS 0x0358 26 #define MSC01_BIU_MCBAS1L_OFS 0x0388 27 #define MSC01_BIU_MCMSK1L_OFS 0x0398 28 #define MSC01_BIU_MCBAS2L_OFS 0x03c8 29 #define MSC01_BIU_MCMSK2L_OFS 0x03d8 30 31 /* 32 * PCI Bridge 33 */ 34 35 #define MSC01_PCI_SC2PMBASL_OFS 0x0208 36 #define MSC01_PCI_SC2PMMSKL_OFS 0x0218 37 #define MSC01_PCI_SC2PMMAPL_OFS 0x0228 38 #define MSC01_PCI_SC2PIOBASL_OFS 0x0248 39 #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 40 #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 41 #define MSC01_PCI_P2SCMSKL_OFS 0x0308 42 #define MSC01_PCI_P2SCMAPL_OFS 0x0318 43 #define MSC01_PCI_INTSTAT_OFS 0x0608 44 #define MSC01_PCI_CFGADDR_OFS 0x0610 45 #define MSC01_PCI_CFGDATA_OFS 0x0618 46 #define MSC01_PCI_HEAD0_OFS 0x2000 47 #define MSC01_PCI_HEAD1_OFS 0x2008 48 #define MSC01_PCI_HEAD2_OFS 0x2010 49 #define MSC01_PCI_HEAD3_OFS 0x2018 50 #define MSC01_PCI_HEAD4_OFS 0x2020 51 #define MSC01_PCI_HEAD5_OFS 0x2028 52 #define MSC01_PCI_HEAD6_OFS 0x2030 53 #define MSC01_PCI_HEAD7_OFS 0x2038 54 #define MSC01_PCI_HEAD8_OFS 0x2040 55 #define MSC01_PCI_HEAD9_OFS 0x2048 56 #define MSC01_PCI_HEAD10_OFS 0x2050 57 #define MSC01_PCI_HEAD11_OFS 0x2058 58 #define MSC01_PCI_HEAD12_OFS 0x2060 59 #define MSC01_PCI_HEAD13_OFS 0x2068 60 #define MSC01_PCI_HEAD14_OFS 0x2070 61 #define MSC01_PCI_HEAD15_OFS 0x2078 62 #define MSC01_PCI_BAR0_OFS 0x2220 63 #define MSC01_PCI_CFG_OFS 0x2380 64 #define MSC01_PCI_SWAP_OFS 0x2388 65 66 #define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 67 #define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 68 69 #define MSC01_PCI_INTSTAT_TA_SHF 6 70 #define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) 71 #define MSC01_PCI_INTSTAT_MA_SHF 7 72 #define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) 73 74 #define MSC01_PCI_CFGADDR_BNUM_SHF 16 75 #define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) 76 #define MSC01_PCI_CFGADDR_DNUM_SHF 11 77 #define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) 78 #define MSC01_PCI_CFGADDR_FNUM_SHF 8 79 #define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) 80 #define MSC01_PCI_CFGADDR_RNUM_SHF 2 81 #define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) 82 83 #define MSC01_PCI_HEAD0_VENDORID_SHF 0 84 #define MSC01_PCI_HEAD0_DEVICEID_SHF 16 85 86 #define MSC01_PCI_HEAD2_REV_SHF 0 87 #define MSC01_PCI_HEAD2_CLASS_SHF 16 88 89 #define MSC01_PCI_CFG_EN_SHF 15 90 #define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) 91 #define MSC01_PCI_CFG_G_SHF 16 92 #define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) 93 #define MSC01_PCI_CFG_RA_SHF 17 94 #define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) 95 96 #define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 97 #define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 98 99 /* 100 * Peripheral Bus Controller 101 */ 102 103 #define MSC01_PBC_CLKCFG_OFS 0x0100 104 #define MSC01_PBC_CS0CFG_OFS 0x0400 105 #define MSC01_PBC_CS0TIM_OFS 0x0500 106 #define MSC01_PBC_CS0RW_OFS 0x0600 107 108 #define MSC01_PBC_CLKCFG_SHF 0 109 #define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) 110 111 #define MSC01_PBC_CS0CFG_WS_SHF 0 112 #define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) 113 #define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 114 #define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) 115 #define MSC01_PBC_CS0CFG_DTYP_SHF 16 116 #define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) 117 #define MSC01_PBC_CS0CFG_ADM_SHF 20 118 #define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) 119 120 #define MSC01_PBC_CS0TIM_CAT_SHF 0 121 #define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) 122 #define MSC01_PBC_CS0TIM_CDT_SHF 8 123 #define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) 124 125 #define MSC01_PBC_CS0RW_WAT_SHF 0 126 #define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) 127 #define MSC01_PBC_CS0RW_WDT_SHF 8 128 #define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) 129 #define MSC01_PBC_CS0RW_RAT_SHF 16 130 #define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) 131 #define MSC01_PBC_CS0RW_RDT_SHF 24 132 #define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) 133 134 #endif /* __MSC01_H__ */ 135
