1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7 #ifndef _CBUS_H_ 8 #define _CBUS_H_ 9 10 #include "cbus/emac.h" 11 #include "cbus/gpi.h" 12 #include "cbus/bmu.h" 13 #include "cbus/hif.h" 14 #include "cbus/tmu_csr.h" 15 #include "cbus/class_csr.h" 16 #include "cbus/hif_nocpy.h" 17 #include "cbus/util_csr.h" 18 19 #define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR) 20 21 /* PFE Control and Status Register Desciption */ 22 #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) 23 #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) 24 #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) 25 #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) 26 #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) 27 #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) 28 #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) 29 #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) 30 #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) 31 #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) 32 #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) 33 #define LMEM_SIZE 0x10000 34 #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) 35 #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) 36 #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) 37 #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) 38 #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) 39 #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) 40 41 /* 42 * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 43 * XXX_MEM_ACCESS_ADDR register bit definitions. 44 */ 45 /* Internal Memory Write. */ 46 #define PE_MEM_ACCESS_WRITE BIT(31) 47 /* Internal Memory Read. */ 48 #define PE_MEM_ACCESS_READ (0 << 31) 49 50 #define PE_MEM_ACCESS_IMEM BIT(15) 51 #define PE_MEM_ACCESS_DMEM BIT(16) 52 53 /* Byte Enables of the Internal memory access. These are interpred in BE */ 54 #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \ 55 - (offset) - (size)))\ 56 & 0xf) << 24) 57 58 /* PFE cores states */ 59 #define CORE_DISABLE 0x00000000 60 #define CORE_ENABLE 0x00000001 61 #define CORE_SW_RESET 0x00000002 62 63 /* LMEM defines */ 64 #define LMEM_HDR_SIZE 0x0010 65 #define LMEM_BUF_SIZE_LN2 0x7 66 #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) 67 68 /* DDR defines */ 69 #define DDR_HDR_SIZE 0x0100 70 #define DDR_BUF_SIZE_LN2 0xb 71 #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) 72 73 /* Clock generation through PLL */ 74 #define PLL_CLK_EN 1 75 76 #endif /* _CBUS_H_ */ 77
