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      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * Copyright 2015-2016 Freescale Semiconductor, Inc.
      4  * Copyright 2017 NXP
      5  */
      6 
      7 #ifndef _CLASS_CSR_H_
      8 #define _CLASS_CSR_H_
      9 
     10 /*
     11  * @file class_csr.h.
     12  * class_csr - block containing all the classifier control and status register.
     13  * Mapped on CBUS and accessible from all PE's and ARM.
     14  */
     15 #define CLASS_VERSION			(CLASS_CSR_BASE_ADDR + 0x000)
     16 #define CLASS_TX_CTRL			(CLASS_CSR_BASE_ADDR + 0x004)
     17 #define CLASS_INQ_PKTPTR		(CLASS_CSR_BASE_ADDR + 0x010)
     18 /* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
     19 #define CLASS_HDR_SIZE			(CLASS_CSR_BASE_ADDR + 0x014)
     20 /* LMEM header size for the Classifier block.
     21  * Data in the LMEM is written from this offset.
     22  */
     23 #define CLASS_HDR_SIZE_LMEM(off)	((off) & 0x3f)
     24 /* DDR header size for the Classifier block.
     25  * Data in the DDR is written from this offset.
     26  */
     27 #define CLASS_HDR_SIZE_DDR(off)		(((off) & 0x1ff) << 16)
     28 
     29 /* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
     30 #define CLASS_PE0_QB_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x020)
     31 /* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
     32 #define CLASS_PE0_QB_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x024)
     33 
     34 /* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
     35 #define CLASS_PE0_RO_DM_ADDR0		(CLASS_CSR_BASE_ADDR + 0x060)
     36 /* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
     37 #define CLASS_PE0_RO_DM_ADDR1		(CLASS_CSR_BASE_ADDR + 0x064)
     38 
     39 /*
     40  * @name Class PE memory access. Allows external PE's and HOST to
     41  * read/write PMEM/DMEM memory ranges for each classifier PE.
     42  */
     43 #define CLASS_MEM_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x100)
     44 /* Internal Memory Access Write Data [31:0] */
     45 #define CLASS_MEM_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x104)
     46 /* Internal Memory Access Read Data [31:0] */
     47 #define CLASS_MEM_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x108)
     48 #define CLASS_TM_INQ_ADDR		(CLASS_CSR_BASE_ADDR + 0x114)
     49 #define CLASS_PE_STATUS			(CLASS_CSR_BASE_ADDR + 0x118)
     50 
     51 #define CLASS_PE_SYS_CLK_RATIO		(CLASS_CSR_BASE_ADDR + 0x200)
     52 #define CLASS_AFULL_THRES		(CLASS_CSR_BASE_ADDR + 0x204)
     53 #define CLASS_GAP_BETWEEN_READS		(CLASS_CSR_BASE_ADDR + 0x208)
     54 #define CLASS_MAX_BUF_CNT		(CLASS_CSR_BASE_ADDR + 0x20c)
     55 #define CLASS_TSQ_FIFO_THRES		(CLASS_CSR_BASE_ADDR + 0x210)
     56 #define CLASS_TSQ_MAX_CNT		(CLASS_CSR_BASE_ADDR + 0x214)
     57 #define CLASS_IRAM_DATA_0		(CLASS_CSR_BASE_ADDR + 0x218)
     58 #define CLASS_IRAM_DATA_1		(CLASS_CSR_BASE_ADDR + 0x21c)
     59 #define CLASS_IRAM_DATA_2		(CLASS_CSR_BASE_ADDR + 0x220)
     60 #define CLASS_IRAM_DATA_3		(CLASS_CSR_BASE_ADDR + 0x224)
     61 
     62 #define CLASS_BUS_ACCESS_ADDR		(CLASS_CSR_BASE_ADDR + 0x228)
     63 /* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
     64 #define CLASS_BUS_ACCESS_ADDR_MASK	(0x0001FFFF)
     65 
     66 #define CLASS_BUS_ACCESS_WDATA		(CLASS_CSR_BASE_ADDR + 0x22c)
     67 #define CLASS_BUS_ACCESS_RDATA		(CLASS_CSR_BASE_ADDR + 0x230)
     68 
     69 /*
     70  * (route_entry_size[9:0], route_hash_size[23:16]
     71  * (this is actually ln2(size)))
     72  */
     73 #define CLASS_ROUTE_HASH_ENTRY_SIZE	(CLASS_CSR_BASE_ADDR + 0x234)
     74 #define CLASS_ROUTE_ENTRY_SIZE(size)	 ((size) & 0x1ff)
     75 #define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
     76 
     77 #define CLASS_ROUTE_TABLE_BASE		(CLASS_CSR_BASE_ADDR + 0x238)
     78 #define CLASS_ROUTE_MULTI		(CLASS_CSR_BASE_ADDR + 0x23c)
     79 #define CLASS_SMEM_OFFSET		(CLASS_CSR_BASE_ADDR + 0x240)
     80 #define CLASS_LMEM_BUF_SIZE		(CLASS_CSR_BASE_ADDR + 0x244)
     81 #define CLASS_VLAN_ID			(CLASS_CSR_BASE_ADDR + 0x248)
     82 #define CLASS_BMU1_BUF_FREE		(CLASS_CSR_BASE_ADDR + 0x24c)
     83 #define CLASS_USE_TMU_INQ		(CLASS_CSR_BASE_ADDR + 0x250)
     84 #define CLASS_VLAN_ID1			(CLASS_CSR_BASE_ADDR + 0x254)
     85 
     86 #define CLASS_BUS_ACCESS_BASE		(CLASS_CSR_BASE_ADDR + 0x258)
     87 /* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
     88 #define CLASS_BUS_ACCESS_BASE_MASK	(0xFF000000)
     89 
     90 #define CLASS_HIF_PARSE			(CLASS_CSR_BASE_ADDR + 0x25c)
     91 
     92 #define CLASS_HOST_PE0_GP		(CLASS_CSR_BASE_ADDR + 0x260)
     93 #define CLASS_PE0_GP			(CLASS_CSR_BASE_ADDR + 0x264)
     94 #define CLASS_HOST_PE1_GP		(CLASS_CSR_BASE_ADDR + 0x268)
     95 #define CLASS_PE1_GP			(CLASS_CSR_BASE_ADDR + 0x26c)
     96 #define CLASS_HOST_PE2_GP		(CLASS_CSR_BASE_ADDR + 0x270)
     97 #define CLASS_PE2_GP			(CLASS_CSR_BASE_ADDR + 0x274)
     98 #define CLASS_HOST_PE3_GP		(CLASS_CSR_BASE_ADDR + 0x278)
     99 #define CLASS_PE3_GP			(CLASS_CSR_BASE_ADDR + 0x27c)
    100 #define CLASS_HOST_PE4_GP		(CLASS_CSR_BASE_ADDR + 0x280)
    101 #define CLASS_PE4_GP			(CLASS_CSR_BASE_ADDR + 0x284)
    102 #define CLASS_HOST_PE5_GP		(CLASS_CSR_BASE_ADDR + 0x288)
    103 #define CLASS_PE5_GP			(CLASS_CSR_BASE_ADDR + 0x28c)
    104 
    105 #define CLASS_PE_INT_SRC		(CLASS_CSR_BASE_ADDR + 0x290)
    106 #define CLASS_PE_INT_ENABLE		(CLASS_CSR_BASE_ADDR + 0x294)
    107 
    108 #define CLASS_TPID0_TPID1		(CLASS_CSR_BASE_ADDR + 0x298)
    109 #define CLASS_TPID2			(CLASS_CSR_BASE_ADDR + 0x29c)
    110 
    111 #define CLASS_L4_CHKSUM_ADDR		(CLASS_CSR_BASE_ADDR + 0x2a0)
    112 
    113 #define CLASS_PE0_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a4)
    114 #define CLASS_PE1_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2a8)
    115 #define CLASS_PE2_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2ac)
    116 #define CLASS_PE3_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b0)
    117 #define CLASS_PE4_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b4)
    118 #define CLASS_PE5_DEBUG			(CLASS_CSR_BASE_ADDR + 0x2b8)
    119 
    120 #define CLASS_STATE			(CLASS_CSR_BASE_ADDR + 0x2bc)
    121 #define CLASS_AXI_CTRL			(CLASS_CSR_BASE_ADDR + 0x2d0)
    122 
    123 /* CLASS defines */
    124 #define CLASS_PBUF_SIZE			0x100	/* Fixed by hardware */
    125 #define CLASS_PBUF_HEADER_OFFSET	0x80	/* Can be configured */
    126 
    127 #define CLASS_PBUF0_BASE_ADDR		0x000	/* Can be configured */
    128 /* Can be configured */
    129 #define CLASS_PBUF1_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
    130 /* Can be configured */
    131 #define CLASS_PBUF2_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
    132 /* Can be configured */
    133 #define CLASS_PBUF3_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
    134 
    135 #define CLASS_PBUF0_HEADER_BASE_ADDR	(CLASS_PBUF0_BASE_ADDR +\
    136 						CLASS_PBUF_HEADER_OFFSET)
    137 #define CLASS_PBUF1_HEADER_BASE_ADDR	(CLASS_PBUF1_BASE_ADDR +\
    138 						CLASS_PBUF_HEADER_OFFSET)
    139 #define CLASS_PBUF2_HEADER_BASE_ADDR	(CLASS_PBUF2_BASE_ADDR +\
    140 						CLASS_PBUF_HEADER_OFFSET)
    141 #define CLASS_PBUF3_HEADER_BASE_ADDR	(CLASS_PBUF3_BASE_ADDR +\
    142 						CLASS_PBUF_HEADER_OFFSET)
    143 
    144 #define CLASS_PE0_RO_DM_ADDR0_VAL	((CLASS_PBUF1_BASE_ADDR << 16) |\
    145 						CLASS_PBUF0_BASE_ADDR)
    146 #define CLASS_PE0_RO_DM_ADDR1_VAL	((CLASS_PBUF3_BASE_ADDR << 16) |\
    147 						CLASS_PBUF2_BASE_ADDR)
    148 
    149 #define CLASS_PE0_QB_DM_ADDR0_VAL	((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
    150 						| CLASS_PBUF0_HEADER_BASE_ADDR)
    151 #define CLASS_PE0_QB_DM_ADDR1_VAL	((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
    152 						| CLASS_PBUF2_HEADER_BASE_ADDR)
    153 
    154 #define CLASS_ROUTE_SIZE		128
    155 #define CLASS_ROUTE_HASH_BITS		20
    156 #define CLASS_ROUTE_HASH_MASK		(BIT(CLASS_ROUTE_HASH_BITS) - 1)
    157 
    158 #define TWO_LEVEL_ROUTE		BIT(0)
    159 #define PHYNO_IN_HASH		BIT(1)
    160 #define HW_ROUTE_FETCH		BIT(3)
    161 #define HW_BRIDGE_FETCH		BIT(5)
    162 #define IP_ALIGNED		BIT(6)
    163 #define ARC_HIT_CHECK_EN	BIT(7)
    164 #define CLASS_TOE		BIT(11)
    165 #define HASH_CRC_PORT		BIT(12)
    166 #define HASH_CRC_IP		BIT(13)
    167 #define HASH_CRC_PORT_IP	GENMASK(13, 12)
    168 #define QB2BUS_LE		BIT(15)
    169 
    170 #define	TCP_CHKSUM_DROP		BIT(0)
    171 #define	UDP_CHKSUM_DROP		BIT(1)
    172 #define	IPV4_CHKSUM_DROP	BIT(9)
    173 
    174 struct class_cfg {
    175 	u32 route_table_baseaddr;
    176 	u32 route_table_hash_bits;
    177 };
    178 
    179 #endif /* _CLASS_CSR_H_ */
    180