1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7 #ifndef _GPI_H_ 8 #define _GPI_H_ 9 10 #define GPI_VERSION 0x00 11 #define GPI_CTRL 0x04 12 #define GPI_RX_CONFIG 0x08 13 #define GPI_HDR_SIZE 0x0c 14 #define GPI_BUF_SIZE 0x10 15 #define GPI_LMEM_ALLOC_ADDR 0x14 16 #define GPI_LMEM_FREE_ADDR 0x18 17 #define GPI_DDR_ALLOC_ADDR 0x1c 18 #define GPI_DDR_FREE_ADDR 0x20 19 #define GPI_CLASS_ADDR 0x24 20 #define GPI_DRX_FIFO 0x28 21 #define GPI_TRX_FIFO 0x2c 22 #define GPI_INQ_PKTPTR 0x30 23 #define GPI_DDR_DATA_OFFSET 0x34 24 #define GPI_LMEM_DATA_OFFSET 0x38 25 #define GPI_TMLF_TX 0x4c 26 #define GPI_DTX_ASEQ 0x50 27 #define GPI_FIFO_STATUS 0x54 28 #define GPI_FIFO_DEBUG 0x58 29 #define GPI_TX_PAUSE_TIME 0x5c 30 #define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 31 #define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 32 #define GPI_TOE_CHKSUM_EN 0x68 33 #define GPI_OVERRUN_DROPCNT 0x6c 34 #define GPI_AXI_CTRL 0x70 35 36 struct gpi_cfg { 37 u32 lmem_rtry_cnt; 38 u32 tmlf_txthres; 39 u32 aseq_len; 40 }; 41 42 /* GPI commons defines */ 43 #define GPI_LMEM_BUF_EN 0x1 44 #define GPI_DDR_BUF_EN 0x1 45 46 /* EGPI 1 defines */ 47 #define EGPI1_LMEM_RTRY_CNT 0x40 48 #define EGPI1_TMLF_TXTHRES 0xBC 49 #define EGPI1_ASEQ_LEN 0x50 50 51 /* EGPI 2 defines */ 52 #define EGPI2_LMEM_RTRY_CNT 0x40 53 #define EGPI2_TMLF_TXTHRES 0xBC 54 #define EGPI2_ASEQ_LEN 0x40 55 56 /* HGPI defines */ 57 #define HGPI_LMEM_RTRY_CNT 0x40 58 #define HGPI_TMLF_TXTHRES 0xBC 59 #define HGPI_ASEQ_LEN 0x40 60 61 #endif /* _GPI_H_ */ 62
