1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Tests for the driver model pmic API 4 * 5 * Copyright (c) 2015 Samsung Electronics 6 * Przemyslaw Marczak <p.marczak (at) samsung.com> 7 */ 8 9 #include <common.h> 10 #include <errno.h> 11 #include <dm.h> 12 #include <fdtdec.h> 13 #include <malloc.h> 14 #include <dm/device-internal.h> 15 #include <dm/root.h> 16 #include <dm/util.h> 17 #include <dm/test.h> 18 #include <dm/uclass-internal.h> 19 #include <power/pmic.h> 20 #include <power/sandbox_pmic.h> 21 #include <test/ut.h> 22 #include <fsl_pmic.h> 23 24 /* Test PMIC get method */ 25 26 static inline int power_pmic_get(struct unit_test_state *uts, char *name) 27 { 28 struct udevice *dev; 29 30 ut_assertok(pmic_get(name, &dev)); 31 ut_assertnonnull(dev); 32 33 /* Check PMIC's name */ 34 ut_asserteq_str(name, dev->name); 35 36 return 0; 37 } 38 39 /* Test PMIC get method */ 40 static int dm_test_power_pmic_get(struct unit_test_state *uts) 41 { 42 power_pmic_get(uts, "sandbox_pmic"); 43 44 return 0; 45 } 46 DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT); 47 48 /* PMIC get method - MC34708 - for 3 bytes transmission */ 49 static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts) 50 { 51 power_pmic_get(uts, "pmic@41"); 52 53 return 0; 54 } 55 56 DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT); 57 58 /* Test PMIC I/O */ 59 static int dm_test_power_pmic_io(struct unit_test_state *uts) 60 { 61 const char *name = "sandbox_pmic"; 62 uint8_t out_buffer, in_buffer; 63 struct udevice *dev; 64 int reg_count, i; 65 66 ut_assertok(pmic_get(name, &dev)); 67 68 reg_count = pmic_reg_count(dev); 69 ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT); 70 71 /* 72 * Test PMIC I/O - write and read a loop counter. 73 * usually we can't write to all PMIC's registers in the real hardware, 74 * but we can to the sandbox pmic. 75 */ 76 for (i = 0; i < reg_count; i++) { 77 out_buffer = i; 78 ut_assertok(pmic_write(dev, i, &out_buffer, 1)); 79 ut_assertok(pmic_read(dev, i, &in_buffer, 1)); 80 ut_asserteq(out_buffer, in_buffer); 81 } 82 83 return 0; 84 } 85 DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT); 86 87 #define MC34708_PMIC_REG_COUNT 64 88 #define MC34708_PMIC_TEST_VAL 0x125534 89 static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts) 90 { 91 struct udevice *dev; 92 int reg_count; 93 94 ut_assertok(pmic_get("pmic@41", &dev)); 95 96 /* Check number of PMIC registers */ 97 reg_count = pmic_reg_count(dev); 98 ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT); 99 100 return 0; 101 } 102 103 DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT); 104 105 static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts) 106 { 107 struct udevice *dev; 108 int val; 109 110 ut_assertok(pmic_get("pmic@41", &dev)); 111 112 /* Check if single 3 byte read is successful */ 113 val = pmic_reg_read(dev, REG_POWER_CTL2); 114 ut_asserteq(val, 0x422100); 115 116 /* Check if RW works */ 117 val = 0; 118 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val)); 119 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL)); 120 val = pmic_reg_read(dev, REG_RTC_TIME); 121 ut_asserteq(val, MC34708_PMIC_TEST_VAL); 122 123 pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9); 124 val = pmic_reg_read(dev, REG_POWER_CTL2); 125 ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9)); 126 127 return 0; 128 } 129 130 DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT); 131
