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      1 // Copyright 2014 the V8 project authors. All rights reserved.
      2 // Use of this source code is governed by a BSD-style license that can be
      3 // found in the LICENSE file.
      4 
      5 #ifndef V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
      6 #define V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
      7 
      8 namespace v8 {
      9 namespace internal {
     10 namespace compiler {
     11 
     12 // PPC-specific opcodes that specify which assembly sequence to emit.
     13 // Most opcodes specify a single instruction.
     14 #define TARGET_ARCH_OPCODE_LIST(V) \
     15   V(PPC_And)                       \
     16   V(PPC_AndComplement)             \
     17   V(PPC_Or)                        \
     18   V(PPC_OrComplement)              \
     19   V(PPC_Xor)                       \
     20   V(PPC_ShiftLeft32)               \
     21   V(PPC_ShiftLeft64)               \
     22   V(PPC_ShiftLeftPair)             \
     23   V(PPC_ShiftRight32)              \
     24   V(PPC_ShiftRight64)              \
     25   V(PPC_ShiftRightPair)            \
     26   V(PPC_ShiftRightAlg32)           \
     27   V(PPC_ShiftRightAlg64)           \
     28   V(PPC_ShiftRightAlgPair)         \
     29   V(PPC_RotRight32)                \
     30   V(PPC_RotRight64)                \
     31   V(PPC_Not)                       \
     32   V(PPC_RotLeftAndMask32)          \
     33   V(PPC_RotLeftAndClear64)         \
     34   V(PPC_RotLeftAndClearLeft64)     \
     35   V(PPC_RotLeftAndClearRight64)    \
     36   V(PPC_Add32)                     \
     37   V(PPC_Add64)                     \
     38   V(PPC_AddWithOverflow32)         \
     39   V(PPC_AddPair)                   \
     40   V(PPC_AddDouble)                 \
     41   V(PPC_Sub)                       \
     42   V(PPC_SubWithOverflow32)         \
     43   V(PPC_SubPair)                   \
     44   V(PPC_SubDouble)                 \
     45   V(PPC_Mul32)                     \
     46   V(PPC_Mul32WithHigh32)           \
     47   V(PPC_Mul64)                     \
     48   V(PPC_MulHigh32)                 \
     49   V(PPC_MulHighU32)                \
     50   V(PPC_MulPair)                   \
     51   V(PPC_MulDouble)                 \
     52   V(PPC_Div32)                     \
     53   V(PPC_Div64)                     \
     54   V(PPC_DivU32)                    \
     55   V(PPC_DivU64)                    \
     56   V(PPC_DivDouble)                 \
     57   V(PPC_Mod32)                     \
     58   V(PPC_Mod64)                     \
     59   V(PPC_ModU32)                    \
     60   V(PPC_ModU64)                    \
     61   V(PPC_ModDouble)                 \
     62   V(PPC_Neg)                       \
     63   V(PPC_NegDouble)                 \
     64   V(PPC_SqrtDouble)                \
     65   V(PPC_FloorDouble)               \
     66   V(PPC_CeilDouble)                \
     67   V(PPC_TruncateDouble)            \
     68   V(PPC_RoundDouble)               \
     69   V(PPC_MaxDouble)                 \
     70   V(PPC_MinDouble)                 \
     71   V(PPC_AbsDouble)                 \
     72   V(PPC_Cntlz32)                   \
     73   V(PPC_Cntlz64)                   \
     74   V(PPC_Popcnt32)                  \
     75   V(PPC_Popcnt64)                  \
     76   V(PPC_Cmp32)                     \
     77   V(PPC_Cmp64)                     \
     78   V(PPC_CmpDouble)                 \
     79   V(PPC_Tst32)                     \
     80   V(PPC_Tst64)                     \
     81   V(PPC_Push)                      \
     82   V(PPC_PushFrame)                 \
     83   V(PPC_StoreToStackSlot)          \
     84   V(PPC_ExtendSignWord8)           \
     85   V(PPC_ExtendSignWord16)          \
     86   V(PPC_ExtendSignWord32)          \
     87   V(PPC_Uint32ToUint64)            \
     88   V(PPC_Int64ToInt32)              \
     89   V(PPC_Int64ToFloat32)            \
     90   V(PPC_Int64ToDouble)             \
     91   V(PPC_Uint64ToFloat32)           \
     92   V(PPC_Uint64ToDouble)            \
     93   V(PPC_Int32ToFloat32)            \
     94   V(PPC_Int32ToDouble)             \
     95   V(PPC_Uint32ToFloat32)           \
     96   V(PPC_Uint32ToDouble)            \
     97   V(PPC_Float32ToDouble)           \
     98   V(PPC_Float64SilenceNaN)         \
     99   V(PPC_DoubleToInt32)             \
    100   V(PPC_DoubleToUint32)            \
    101   V(PPC_DoubleToInt64)             \
    102   V(PPC_DoubleToUint64)            \
    103   V(PPC_DoubleToFloat32)           \
    104   V(PPC_DoubleExtractLowWord32)    \
    105   V(PPC_DoubleExtractHighWord32)   \
    106   V(PPC_DoubleInsertLowWord32)     \
    107   V(PPC_DoubleInsertHighWord32)    \
    108   V(PPC_DoubleConstruct)           \
    109   V(PPC_BitcastInt32ToFloat32)     \
    110   V(PPC_BitcastFloat32ToInt32)     \
    111   V(PPC_BitcastInt64ToDouble)      \
    112   V(PPC_BitcastDoubleToInt64)      \
    113   V(PPC_LoadWordS8)                \
    114   V(PPC_LoadWordU8)                \
    115   V(PPC_LoadWordS16)               \
    116   V(PPC_LoadWordU16)               \
    117   V(PPC_LoadWordS32)               \
    118   V(PPC_LoadWordU32)               \
    119   V(PPC_LoadWord64)                \
    120   V(PPC_LoadFloat32)               \
    121   V(PPC_LoadDouble)                \
    122   V(PPC_StoreWord8)                \
    123   V(PPC_StoreWord16)               \
    124   V(PPC_StoreWord32)               \
    125   V(PPC_StoreWord64)               \
    126   V(PPC_StoreFloat32)              \
    127   V(PPC_StoreDouble)               \
    128   V(PPC_ByteRev32)                 \
    129   V(PPC_ByteRev64)
    130 
    131 // Addressing modes represent the "shape" of inputs to an instruction.
    132 // Many instructions support multiple addressing modes. Addressing modes
    133 // are encoded into the InstructionCode of the instruction and tell the
    134 // code generator after register allocation which assembler method to call.
    135 //
    136 // We use the following local notation for addressing modes:
    137 //
    138 // R = register
    139 // O = register or stack slot
    140 // D = double register
    141 // I = immediate (handle, external, int32)
    142 // MRI = [register + immediate]
    143 // MRR = [register + register]
    144 #define TARGET_ADDRESSING_MODE_LIST(V) \
    145   V(MRI) /* [%r0 + K] */               \
    146   V(MRR) /* [%r0 + %r1] */
    147 
    148 }  // namespace compiler
    149 }  // namespace internal
    150 }  // namespace v8
    151 
    152 #endif  // V8_COMPILER_PPC_INSTRUCTION_CODES_PPC_H_
    153