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      1 // Copyright 2015, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_ASSEMBLER_COND_DT_DRT_DRD_DRN_DRM_FLOAT_F32_ONLY_VCGE_A32_H_
     35 #define VIXL_ASSEMBLER_COND_DT_DRT_DRD_DRN_DRM_FLOAT_F32_ONLY_VCGE_A32_H_
     36 
     37 const byte kInstruction_vcge_F32_d1_d2_d30[] = {
     38   0x2e, 0x1e, 0x02, 0xf3 // vcge F32 d1 d2 d30
     39 };
     40 const byte kInstruction_vcge_F32_d12_d5_d13[] = {
     41   0x0d, 0xce, 0x05, 0xf3 // vcge F32 d12 d5 d13
     42 };
     43 const byte kInstruction_vcge_F32_d3_d16_d2[] = {
     44   0x82, 0x3e, 0x00, 0xf3 // vcge F32 d3 d16 d2
     45 };
     46 const byte kInstruction_vcge_F32_d21_d26_d7[] = {
     47   0x87, 0x5e, 0x4a, 0xf3 // vcge F32 d21 d26 d7
     48 };
     49 const byte kInstruction_vcge_F32_d30_d1_d16[] = {
     50   0x20, 0xee, 0x41, 0xf3 // vcge F32 d30 d1 d16
     51 };
     52 const byte kInstruction_vcge_F32_d17_d8_d6[] = {
     53   0x06, 0x1e, 0x48, 0xf3 // vcge F32 d17 d8 d6
     54 };
     55 const byte kInstruction_vcge_F32_d26_d1_d7[] = {
     56   0x07, 0xae, 0x41, 0xf3 // vcge F32 d26 d1 d7
     57 };
     58 const byte kInstruction_vcge_F32_d17_d6_d28[] = {
     59   0x2c, 0x1e, 0x46, 0xf3 // vcge F32 d17 d6 d28
     60 };
     61 const byte kInstruction_vcge_F32_d30_d6_d27[] = {
     62   0x2b, 0xee, 0x46, 0xf3 // vcge F32 d30 d6 d27
     63 };
     64 const byte kInstruction_vcge_F32_d6_d13_d11[] = {
     65   0x0b, 0x6e, 0x0d, 0xf3 // vcge F32 d6 d13 d11
     66 };
     67 const byte kInstruction_vcge_F32_d30_d17_d15[] = {
     68   0x8f, 0xee, 0x41, 0xf3 // vcge F32 d30 d17 d15
     69 };
     70 const byte kInstruction_vcge_F32_d10_d8_d14[] = {
     71   0x0e, 0xae, 0x08, 0xf3 // vcge F32 d10 d8 d14
     72 };
     73 const byte kInstruction_vcge_F32_d17_d4_d0[] = {
     74   0x00, 0x1e, 0x44, 0xf3 // vcge F32 d17 d4 d0
     75 };
     76 const byte kInstruction_vcge_F32_d25_d5_d14[] = {
     77   0x0e, 0x9e, 0x45, 0xf3 // vcge F32 d25 d5 d14
     78 };
     79 const byte kInstruction_vcge_F32_d30_d16_d0[] = {
     80   0x80, 0xee, 0x40, 0xf3 // vcge F32 d30 d16 d0
     81 };
     82 const byte kInstruction_vcge_F32_d22_d21_d2[] = {
     83   0x82, 0x6e, 0x45, 0xf3 // vcge F32 d22 d21 d2
     84 };
     85 const byte kInstruction_vcge_F32_d15_d10_d12[] = {
     86   0x0c, 0xfe, 0x0a, 0xf3 // vcge F32 d15 d10 d12
     87 };
     88 const byte kInstruction_vcge_F32_d6_d26_d20[] = {
     89   0xa4, 0x6e, 0x0a, 0xf3 // vcge F32 d6 d26 d20
     90 };
     91 const byte kInstruction_vcge_F32_d2_d7_d6[] = {
     92   0x06, 0x2e, 0x07, 0xf3 // vcge F32 d2 d7 d6
     93 };
     94 const byte kInstruction_vcge_F32_d27_d13_d30[] = {
     95   0x2e, 0xbe, 0x4d, 0xf3 // vcge F32 d27 d13 d30
     96 };
     97 const byte kInstruction_vcge_F32_d6_d12_d13[] = {
     98   0x0d, 0x6e, 0x0c, 0xf3 // vcge F32 d6 d12 d13
     99 };
    100 const byte kInstruction_vcge_F32_d6_d17_d17[] = {
    101   0xa1, 0x6e, 0x01, 0xf3 // vcge F32 d6 d17 d17
    102 };
    103 const byte kInstruction_vcge_F32_d18_d7_d6[] = {
    104   0x06, 0x2e, 0x47, 0xf3 // vcge F32 d18 d7 d6
    105 };
    106 const byte kInstruction_vcge_F32_d24_d18_d8[] = {
    107   0x88, 0x8e, 0x42, 0xf3 // vcge F32 d24 d18 d8
    108 };
    109 const byte kInstruction_vcge_F32_d27_d3_d3[] = {
    110   0x03, 0xbe, 0x43, 0xf3 // vcge F32 d27 d3 d3
    111 };
    112 const byte kInstruction_vcge_F32_d20_d12_d4[] = {
    113   0x04, 0x4e, 0x4c, 0xf3 // vcge F32 d20 d12 d4
    114 };
    115 const byte kInstruction_vcge_F32_d16_d23_d26[] = {
    116   0xaa, 0x0e, 0x47, 0xf3 // vcge F32 d16 d23 d26
    117 };
    118 const byte kInstruction_vcge_F32_d14_d24_d11[] = {
    119   0x8b, 0xee, 0x08, 0xf3 // vcge F32 d14 d24 d11
    120 };
    121 const byte kInstruction_vcge_F32_d14_d29_d28[] = {
    122   0xac, 0xee, 0x0d, 0xf3 // vcge F32 d14 d29 d28
    123 };
    124 const byte kInstruction_vcge_F32_d20_d16_d11[] = {
    125   0x8b, 0x4e, 0x40, 0xf3 // vcge F32 d20 d16 d11
    126 };
    127 const byte kInstruction_vcge_F32_d28_d21_d9[] = {
    128   0x89, 0xce, 0x45, 0xf3 // vcge F32 d28 d21 d9
    129 };
    130 const byte kInstruction_vcge_F32_d0_d11_d1[] = {
    131   0x01, 0x0e, 0x0b, 0xf3 // vcge F32 d0 d11 d1
    132 };
    133 const byte kInstruction_vcge_F32_d19_d10_d4[] = {
    134   0x04, 0x3e, 0x4a, 0xf3 // vcge F32 d19 d10 d4
    135 };
    136 const byte kInstruction_vcge_F32_d19_d28_d20[] = {
    137   0xa4, 0x3e, 0x4c, 0xf3 // vcge F32 d19 d28 d20
    138 };
    139 const byte kInstruction_vcge_F32_d16_d15_d6[] = {
    140   0x06, 0x0e, 0x4f, 0xf3 // vcge F32 d16 d15 d6
    141 };
    142 const byte kInstruction_vcge_F32_d12_d15_d2[] = {
    143   0x02, 0xce, 0x0f, 0xf3 // vcge F32 d12 d15 d2
    144 };
    145 const byte kInstruction_vcge_F32_d0_d31_d2[] = {
    146   0x82, 0x0e, 0x0f, 0xf3 // vcge F32 d0 d31 d2
    147 };
    148 const byte kInstruction_vcge_F32_d6_d22_d19[] = {
    149   0xa3, 0x6e, 0x06, 0xf3 // vcge F32 d6 d22 d19
    150 };
    151 const byte kInstruction_vcge_F32_d26_d30_d0[] = {
    152   0x80, 0xae, 0x4e, 0xf3 // vcge F32 d26 d30 d0
    153 };
    154 const byte kInstruction_vcge_F32_d5_d19_d18[] = {
    155   0xa2, 0x5e, 0x03, 0xf3 // vcge F32 d5 d19 d18
    156 };
    157 const byte kInstruction_vcge_F32_d7_d3_d3[] = {
    158   0x03, 0x7e, 0x03, 0xf3 // vcge F32 d7 d3 d3
    159 };
    160 const byte kInstruction_vcge_F32_d17_d7_d20[] = {
    161   0x24, 0x1e, 0x47, 0xf3 // vcge F32 d17 d7 d20
    162 };
    163 const byte kInstruction_vcge_F32_d29_d30_d24[] = {
    164   0xa8, 0xde, 0x4e, 0xf3 // vcge F32 d29 d30 d24
    165 };
    166 const byte kInstruction_vcge_F32_d26_d4_d30[] = {
    167   0x2e, 0xae, 0x44, 0xf3 // vcge F32 d26 d4 d30
    168 };
    169 const byte kInstruction_vcge_F32_d30_d27_d9[] = {
    170   0x89, 0xee, 0x4b, 0xf3 // vcge F32 d30 d27 d9
    171 };
    172 const byte kInstruction_vcge_F32_d6_d24_d17[] = {
    173   0xa1, 0x6e, 0x08, 0xf3 // vcge F32 d6 d24 d17
    174 };
    175 const byte kInstruction_vcge_F32_d16_d21_d20[] = {
    176   0xa4, 0x0e, 0x45, 0xf3 // vcge F32 d16 d21 d20
    177 };
    178 const byte kInstruction_vcge_F32_d6_d1_d12[] = {
    179   0x0c, 0x6e, 0x01, 0xf3 // vcge F32 d6 d1 d12
    180 };
    181 const byte kInstruction_vcge_F32_d2_d26_d18[] = {
    182   0xa2, 0x2e, 0x0a, 0xf3 // vcge F32 d2 d26 d18
    183 };
    184 const byte kInstruction_vcge_F32_d21_d31_d7[] = {
    185   0x87, 0x5e, 0x4f, 0xf3 // vcge F32 d21 d31 d7
    186 };
    187 const byte kInstruction_vcge_F32_d8_d18_d17[] = {
    188   0xa1, 0x8e, 0x02, 0xf3 // vcge F32 d8 d18 d17
    189 };
    190 const byte kInstruction_vcge_F32_d18_d11_d8[] = {
    191   0x08, 0x2e, 0x4b, 0xf3 // vcge F32 d18 d11 d8
    192 };
    193 const byte kInstruction_vcge_F32_d25_d14_d5[] = {
    194   0x05, 0x9e, 0x4e, 0xf3 // vcge F32 d25 d14 d5
    195 };
    196 const byte kInstruction_vcge_F32_d0_d9_d5[] = {
    197   0x05, 0x0e, 0x09, 0xf3 // vcge F32 d0 d9 d5
    198 };
    199 const byte kInstruction_vcge_F32_d14_d12_d7[] = {
    200   0x07, 0xee, 0x0c, 0xf3 // vcge F32 d14 d12 d7
    201 };
    202 const byte kInstruction_vcge_F32_d23_d0_d22[] = {
    203   0x26, 0x7e, 0x40, 0xf3 // vcge F32 d23 d0 d22
    204 };
    205 const byte kInstruction_vcge_F32_d23_d31_d10[] = {
    206   0x8a, 0x7e, 0x4f, 0xf3 // vcge F32 d23 d31 d10
    207 };
    208 const byte kInstruction_vcge_F32_d3_d19_d28[] = {
    209   0xac, 0x3e, 0x03, 0xf3 // vcge F32 d3 d19 d28
    210 };
    211 const byte kInstruction_vcge_F32_d9_d26_d15[] = {
    212   0x8f, 0x9e, 0x0a, 0xf3 // vcge F32 d9 d26 d15
    213 };
    214 const byte kInstruction_vcge_F32_d17_d13_d26[] = {
    215   0x2a, 0x1e, 0x4d, 0xf3 // vcge F32 d17 d13 d26
    216 };
    217 const byte kInstruction_vcge_F32_d2_d26_d5[] = {
    218   0x85, 0x2e, 0x0a, 0xf3 // vcge F32 d2 d26 d5
    219 };
    220 const byte kInstruction_vcge_F32_d18_d28_d11[] = {
    221   0x8b, 0x2e, 0x4c, 0xf3 // vcge F32 d18 d28 d11
    222 };
    223 const byte kInstruction_vcge_F32_d20_d10_d2[] = {
    224   0x02, 0x4e, 0x4a, 0xf3 // vcge F32 d20 d10 d2
    225 };
    226 const byte kInstruction_vcge_F32_d19_d3_d9[] = {
    227   0x09, 0x3e, 0x43, 0xf3 // vcge F32 d19 d3 d9
    228 };
    229 const byte kInstruction_vcge_F32_d4_d29_d17[] = {
    230   0xa1, 0x4e, 0x0d, 0xf3 // vcge F32 d4 d29 d17
    231 };
    232 const byte kInstruction_vcge_F32_d22_d1_d31[] = {
    233   0x2f, 0x6e, 0x41, 0xf3 // vcge F32 d22 d1 d31
    234 };
    235 const byte kInstruction_vcge_F32_d29_d2_d17[] = {
    236   0x21, 0xde, 0x42, 0xf3 // vcge F32 d29 d2 d17
    237 };
    238 const byte kInstruction_vcge_F32_d18_d8_d10[] = {
    239   0x0a, 0x2e, 0x48, 0xf3 // vcge F32 d18 d8 d10
    240 };
    241 const byte kInstruction_vcge_F32_d16_d8_d22[] = {
    242   0x26, 0x0e, 0x48, 0xf3 // vcge F32 d16 d8 d22
    243 };
    244 const byte kInstruction_vcge_F32_d0_d27_d19[] = {
    245   0xa3, 0x0e, 0x0b, 0xf3 // vcge F32 d0 d27 d19
    246 };
    247 const byte kInstruction_vcge_F32_d26_d23_d0[] = {
    248   0x80, 0xae, 0x47, 0xf3 // vcge F32 d26 d23 d0
    249 };
    250 const byte kInstruction_vcge_F32_d30_d21_d22[] = {
    251   0xa6, 0xee, 0x45, 0xf3 // vcge F32 d30 d21 d22
    252 };
    253 const byte kInstruction_vcge_F32_d31_d31_d8[] = {
    254   0x88, 0xfe, 0x4f, 0xf3 // vcge F32 d31 d31 d8
    255 };
    256 const byte kInstruction_vcge_F32_d4_d7_d2[] = {
    257   0x02, 0x4e, 0x07, 0xf3 // vcge F32 d4 d7 d2
    258 };
    259 const byte kInstruction_vcge_F32_d8_d22_d31[] = {
    260   0xaf, 0x8e, 0x06, 0xf3 // vcge F32 d8 d22 d31
    261 };
    262 const byte kInstruction_vcge_F32_d27_d3_d14[] = {
    263   0x0e, 0xbe, 0x43, 0xf3 // vcge F32 d27 d3 d14
    264 };
    265 const byte kInstruction_vcge_F32_d11_d26_d6[] = {
    266   0x86, 0xbe, 0x0a, 0xf3 // vcge F32 d11 d26 d6
    267 };
    268 const byte kInstruction_vcge_F32_d20_d24_d4[] = {
    269   0x84, 0x4e, 0x48, 0xf3 // vcge F32 d20 d24 d4
    270 };
    271 const byte kInstruction_vcge_F32_d1_d8_d3[] = {
    272   0x03, 0x1e, 0x08, 0xf3 // vcge F32 d1 d8 d3
    273 };
    274 const byte kInstruction_vcge_F32_d27_d17_d17[] = {
    275   0xa1, 0xbe, 0x41, 0xf3 // vcge F32 d27 d17 d17
    276 };
    277 const byte kInstruction_vcge_F32_d25_d21_d8[] = {
    278   0x88, 0x9e, 0x45, 0xf3 // vcge F32 d25 d21 d8
    279 };
    280 const byte kInstruction_vcge_F32_d6_d0_d15[] = {
    281   0x0f, 0x6e, 0x00, 0xf3 // vcge F32 d6 d0 d15
    282 };
    283 const byte kInstruction_vcge_F32_d4_d10_d9[] = {
    284   0x09, 0x4e, 0x0a, 0xf3 // vcge F32 d4 d10 d9
    285 };
    286 const byte kInstruction_vcge_F32_d13_d26_d11[] = {
    287   0x8b, 0xde, 0x0a, 0xf3 // vcge F32 d13 d26 d11
    288 };
    289 const byte kInstruction_vcge_F32_d7_d6_d18[] = {
    290   0x22, 0x7e, 0x06, 0xf3 // vcge F32 d7 d6 d18
    291 };
    292 const byte kInstruction_vcge_F32_d11_d7_d10[] = {
    293   0x0a, 0xbe, 0x07, 0xf3 // vcge F32 d11 d7 d10
    294 };
    295 const byte kInstruction_vcge_F32_d17_d3_d10[] = {
    296   0x0a, 0x1e, 0x43, 0xf3 // vcge F32 d17 d3 d10
    297 };
    298 const byte kInstruction_vcge_F32_d9_d19_d11[] = {
    299   0x8b, 0x9e, 0x03, 0xf3 // vcge F32 d9 d19 d11
    300 };
    301 const byte kInstruction_vcge_F32_d9_d22_d10[] = {
    302   0x8a, 0x9e, 0x06, 0xf3 // vcge F32 d9 d22 d10
    303 };
    304 const byte kInstruction_vcge_F32_d30_d0_d21[] = {
    305   0x25, 0xee, 0x40, 0xf3 // vcge F32 d30 d0 d21
    306 };
    307 const byte kInstruction_vcge_F32_d13_d1_d15[] = {
    308   0x0f, 0xde, 0x01, 0xf3 // vcge F32 d13 d1 d15
    309 };
    310 const byte kInstruction_vcge_F32_d27_d11_d10[] = {
    311   0x0a, 0xbe, 0x4b, 0xf3 // vcge F32 d27 d11 d10
    312 };
    313 const byte kInstruction_vcge_F32_d7_d26_d9[] = {
    314   0x89, 0x7e, 0x0a, 0xf3 // vcge F32 d7 d26 d9
    315 };
    316 const byte kInstruction_vcge_F32_d1_d12_d21[] = {
    317   0x25, 0x1e, 0x0c, 0xf3 // vcge F32 d1 d12 d21
    318 };
    319 const byte kInstruction_vcge_F32_d26_d28_d30[] = {
    320   0xae, 0xae, 0x4c, 0xf3 // vcge F32 d26 d28 d30
    321 };
    322 const byte kInstruction_vcge_F32_d31_d14_d5[] = {
    323   0x05, 0xfe, 0x4e, 0xf3 // vcge F32 d31 d14 d5
    324 };
    325 const byte kInstruction_vcge_F32_d29_d12_d7[] = {
    326   0x07, 0xde, 0x4c, 0xf3 // vcge F32 d29 d12 d7
    327 };
    328 const byte kInstruction_vcge_F32_d19_d30_d1[] = {
    329   0x81, 0x3e, 0x4e, 0xf3 // vcge F32 d19 d30 d1
    330 };
    331 const byte kInstruction_vcge_F32_d4_d1_d26[] = {
    332   0x2a, 0x4e, 0x01, 0xf3 // vcge F32 d4 d1 d26
    333 };
    334 const byte kInstruction_vcge_F32_d2_d13_d10[] = {
    335   0x0a, 0x2e, 0x0d, 0xf3 // vcge F32 d2 d13 d10
    336 };
    337 const TestResult kReferencevcge[] = {
    338   {
    339     ARRAY_SIZE(kInstruction_vcge_F32_d1_d2_d30),
    340     kInstruction_vcge_F32_d1_d2_d30,
    341   },
    342   {
    343     ARRAY_SIZE(kInstruction_vcge_F32_d12_d5_d13),
    344     kInstruction_vcge_F32_d12_d5_d13,
    345   },
    346   {
    347     ARRAY_SIZE(kInstruction_vcge_F32_d3_d16_d2),
    348     kInstruction_vcge_F32_d3_d16_d2,
    349   },
    350   {
    351     ARRAY_SIZE(kInstruction_vcge_F32_d21_d26_d7),
    352     kInstruction_vcge_F32_d21_d26_d7,
    353   },
    354   {
    355     ARRAY_SIZE(kInstruction_vcge_F32_d30_d1_d16),
    356     kInstruction_vcge_F32_d30_d1_d16,
    357   },
    358   {
    359     ARRAY_SIZE(kInstruction_vcge_F32_d17_d8_d6),
    360     kInstruction_vcge_F32_d17_d8_d6,
    361   },
    362   {
    363     ARRAY_SIZE(kInstruction_vcge_F32_d26_d1_d7),
    364     kInstruction_vcge_F32_d26_d1_d7,
    365   },
    366   {
    367     ARRAY_SIZE(kInstruction_vcge_F32_d17_d6_d28),
    368     kInstruction_vcge_F32_d17_d6_d28,
    369   },
    370   {
    371     ARRAY_SIZE(kInstruction_vcge_F32_d30_d6_d27),
    372     kInstruction_vcge_F32_d30_d6_d27,
    373   },
    374   {
    375     ARRAY_SIZE(kInstruction_vcge_F32_d6_d13_d11),
    376     kInstruction_vcge_F32_d6_d13_d11,
    377   },
    378   {
    379     ARRAY_SIZE(kInstruction_vcge_F32_d30_d17_d15),
    380     kInstruction_vcge_F32_d30_d17_d15,
    381   },
    382   {
    383     ARRAY_SIZE(kInstruction_vcge_F32_d10_d8_d14),
    384     kInstruction_vcge_F32_d10_d8_d14,
    385   },
    386   {
    387     ARRAY_SIZE(kInstruction_vcge_F32_d17_d4_d0),
    388     kInstruction_vcge_F32_d17_d4_d0,
    389   },
    390   {
    391     ARRAY_SIZE(kInstruction_vcge_F32_d25_d5_d14),
    392     kInstruction_vcge_F32_d25_d5_d14,
    393   },
    394   {
    395     ARRAY_SIZE(kInstruction_vcge_F32_d30_d16_d0),
    396     kInstruction_vcge_F32_d30_d16_d0,
    397   },
    398   {
    399     ARRAY_SIZE(kInstruction_vcge_F32_d22_d21_d2),
    400     kInstruction_vcge_F32_d22_d21_d2,
    401   },
    402   {
    403     ARRAY_SIZE(kInstruction_vcge_F32_d15_d10_d12),
    404     kInstruction_vcge_F32_d15_d10_d12,
    405   },
    406   {
    407     ARRAY_SIZE(kInstruction_vcge_F32_d6_d26_d20),
    408     kInstruction_vcge_F32_d6_d26_d20,
    409   },
    410   {
    411     ARRAY_SIZE(kInstruction_vcge_F32_d2_d7_d6),
    412     kInstruction_vcge_F32_d2_d7_d6,
    413   },
    414   {
    415     ARRAY_SIZE(kInstruction_vcge_F32_d27_d13_d30),
    416     kInstruction_vcge_F32_d27_d13_d30,
    417   },
    418   {
    419     ARRAY_SIZE(kInstruction_vcge_F32_d6_d12_d13),
    420     kInstruction_vcge_F32_d6_d12_d13,
    421   },
    422   {
    423     ARRAY_SIZE(kInstruction_vcge_F32_d6_d17_d17),
    424     kInstruction_vcge_F32_d6_d17_d17,
    425   },
    426   {
    427     ARRAY_SIZE(kInstruction_vcge_F32_d18_d7_d6),
    428     kInstruction_vcge_F32_d18_d7_d6,
    429   },
    430   {
    431     ARRAY_SIZE(kInstruction_vcge_F32_d24_d18_d8),
    432     kInstruction_vcge_F32_d24_d18_d8,
    433   },
    434   {
    435     ARRAY_SIZE(kInstruction_vcge_F32_d27_d3_d3),
    436     kInstruction_vcge_F32_d27_d3_d3,
    437   },
    438   {
    439     ARRAY_SIZE(kInstruction_vcge_F32_d20_d12_d4),
    440     kInstruction_vcge_F32_d20_d12_d4,
    441   },
    442   {
    443     ARRAY_SIZE(kInstruction_vcge_F32_d16_d23_d26),
    444     kInstruction_vcge_F32_d16_d23_d26,
    445   },
    446   {
    447     ARRAY_SIZE(kInstruction_vcge_F32_d14_d24_d11),
    448     kInstruction_vcge_F32_d14_d24_d11,
    449   },
    450   {
    451     ARRAY_SIZE(kInstruction_vcge_F32_d14_d29_d28),
    452     kInstruction_vcge_F32_d14_d29_d28,
    453   },
    454   {
    455     ARRAY_SIZE(kInstruction_vcge_F32_d20_d16_d11),
    456     kInstruction_vcge_F32_d20_d16_d11,
    457   },
    458   {
    459     ARRAY_SIZE(kInstruction_vcge_F32_d28_d21_d9),
    460     kInstruction_vcge_F32_d28_d21_d9,
    461   },
    462   {
    463     ARRAY_SIZE(kInstruction_vcge_F32_d0_d11_d1),
    464     kInstruction_vcge_F32_d0_d11_d1,
    465   },
    466   {
    467     ARRAY_SIZE(kInstruction_vcge_F32_d19_d10_d4),
    468     kInstruction_vcge_F32_d19_d10_d4,
    469   },
    470   {
    471     ARRAY_SIZE(kInstruction_vcge_F32_d19_d28_d20),
    472     kInstruction_vcge_F32_d19_d28_d20,
    473   },
    474   {
    475     ARRAY_SIZE(kInstruction_vcge_F32_d16_d15_d6),
    476     kInstruction_vcge_F32_d16_d15_d6,
    477   },
    478   {
    479     ARRAY_SIZE(kInstruction_vcge_F32_d12_d15_d2),
    480     kInstruction_vcge_F32_d12_d15_d2,
    481   },
    482   {
    483     ARRAY_SIZE(kInstruction_vcge_F32_d0_d31_d2),
    484     kInstruction_vcge_F32_d0_d31_d2,
    485   },
    486   {
    487     ARRAY_SIZE(kInstruction_vcge_F32_d6_d22_d19),
    488     kInstruction_vcge_F32_d6_d22_d19,
    489   },
    490   {
    491     ARRAY_SIZE(kInstruction_vcge_F32_d26_d30_d0),
    492     kInstruction_vcge_F32_d26_d30_d0,
    493   },
    494   {
    495     ARRAY_SIZE(kInstruction_vcge_F32_d5_d19_d18),
    496     kInstruction_vcge_F32_d5_d19_d18,
    497   },
    498   {
    499     ARRAY_SIZE(kInstruction_vcge_F32_d7_d3_d3),
    500     kInstruction_vcge_F32_d7_d3_d3,
    501   },
    502   {
    503     ARRAY_SIZE(kInstruction_vcge_F32_d17_d7_d20),
    504     kInstruction_vcge_F32_d17_d7_d20,
    505   },
    506   {
    507     ARRAY_SIZE(kInstruction_vcge_F32_d29_d30_d24),
    508     kInstruction_vcge_F32_d29_d30_d24,
    509   },
    510   {
    511     ARRAY_SIZE(kInstruction_vcge_F32_d26_d4_d30),
    512     kInstruction_vcge_F32_d26_d4_d30,
    513   },
    514   {
    515     ARRAY_SIZE(kInstruction_vcge_F32_d30_d27_d9),
    516     kInstruction_vcge_F32_d30_d27_d9,
    517   },
    518   {
    519     ARRAY_SIZE(kInstruction_vcge_F32_d6_d24_d17),
    520     kInstruction_vcge_F32_d6_d24_d17,
    521   },
    522   {
    523     ARRAY_SIZE(kInstruction_vcge_F32_d16_d21_d20),
    524     kInstruction_vcge_F32_d16_d21_d20,
    525   },
    526   {
    527     ARRAY_SIZE(kInstruction_vcge_F32_d6_d1_d12),
    528     kInstruction_vcge_F32_d6_d1_d12,
    529   },
    530   {
    531     ARRAY_SIZE(kInstruction_vcge_F32_d2_d26_d18),
    532     kInstruction_vcge_F32_d2_d26_d18,
    533   },
    534   {
    535     ARRAY_SIZE(kInstruction_vcge_F32_d21_d31_d7),
    536     kInstruction_vcge_F32_d21_d31_d7,
    537   },
    538   {
    539     ARRAY_SIZE(kInstruction_vcge_F32_d8_d18_d17),
    540     kInstruction_vcge_F32_d8_d18_d17,
    541   },
    542   {
    543     ARRAY_SIZE(kInstruction_vcge_F32_d18_d11_d8),
    544     kInstruction_vcge_F32_d18_d11_d8,
    545   },
    546   {
    547     ARRAY_SIZE(kInstruction_vcge_F32_d25_d14_d5),
    548     kInstruction_vcge_F32_d25_d14_d5,
    549   },
    550   {
    551     ARRAY_SIZE(kInstruction_vcge_F32_d0_d9_d5),
    552     kInstruction_vcge_F32_d0_d9_d5,
    553   },
    554   {
    555     ARRAY_SIZE(kInstruction_vcge_F32_d14_d12_d7),
    556     kInstruction_vcge_F32_d14_d12_d7,
    557   },
    558   {
    559     ARRAY_SIZE(kInstruction_vcge_F32_d23_d0_d22),
    560     kInstruction_vcge_F32_d23_d0_d22,
    561   },
    562   {
    563     ARRAY_SIZE(kInstruction_vcge_F32_d23_d31_d10),
    564     kInstruction_vcge_F32_d23_d31_d10,
    565   },
    566   {
    567     ARRAY_SIZE(kInstruction_vcge_F32_d3_d19_d28),
    568     kInstruction_vcge_F32_d3_d19_d28,
    569   },
    570   {
    571     ARRAY_SIZE(kInstruction_vcge_F32_d9_d26_d15),
    572     kInstruction_vcge_F32_d9_d26_d15,
    573   },
    574   {
    575     ARRAY_SIZE(kInstruction_vcge_F32_d17_d13_d26),
    576     kInstruction_vcge_F32_d17_d13_d26,
    577   },
    578   {
    579     ARRAY_SIZE(kInstruction_vcge_F32_d2_d26_d5),
    580     kInstruction_vcge_F32_d2_d26_d5,
    581   },
    582   {
    583     ARRAY_SIZE(kInstruction_vcge_F32_d18_d28_d11),
    584     kInstruction_vcge_F32_d18_d28_d11,
    585   },
    586   {
    587     ARRAY_SIZE(kInstruction_vcge_F32_d20_d10_d2),
    588     kInstruction_vcge_F32_d20_d10_d2,
    589   },
    590   {
    591     ARRAY_SIZE(kInstruction_vcge_F32_d19_d3_d9),
    592     kInstruction_vcge_F32_d19_d3_d9,
    593   },
    594   {
    595     ARRAY_SIZE(kInstruction_vcge_F32_d4_d29_d17),
    596     kInstruction_vcge_F32_d4_d29_d17,
    597   },
    598   {
    599     ARRAY_SIZE(kInstruction_vcge_F32_d22_d1_d31),
    600     kInstruction_vcge_F32_d22_d1_d31,
    601   },
    602   {
    603     ARRAY_SIZE(kInstruction_vcge_F32_d29_d2_d17),
    604     kInstruction_vcge_F32_d29_d2_d17,
    605   },
    606   {
    607     ARRAY_SIZE(kInstruction_vcge_F32_d18_d8_d10),
    608     kInstruction_vcge_F32_d18_d8_d10,
    609   },
    610   {
    611     ARRAY_SIZE(kInstruction_vcge_F32_d16_d8_d22),
    612     kInstruction_vcge_F32_d16_d8_d22,
    613   },
    614   {
    615     ARRAY_SIZE(kInstruction_vcge_F32_d0_d27_d19),
    616     kInstruction_vcge_F32_d0_d27_d19,
    617   },
    618   {
    619     ARRAY_SIZE(kInstruction_vcge_F32_d26_d23_d0),
    620     kInstruction_vcge_F32_d26_d23_d0,
    621   },
    622   {
    623     ARRAY_SIZE(kInstruction_vcge_F32_d30_d21_d22),
    624     kInstruction_vcge_F32_d30_d21_d22,
    625   },
    626   {
    627     ARRAY_SIZE(kInstruction_vcge_F32_d31_d31_d8),
    628     kInstruction_vcge_F32_d31_d31_d8,
    629   },
    630   {
    631     ARRAY_SIZE(kInstruction_vcge_F32_d4_d7_d2),
    632     kInstruction_vcge_F32_d4_d7_d2,
    633   },
    634   {
    635     ARRAY_SIZE(kInstruction_vcge_F32_d8_d22_d31),
    636     kInstruction_vcge_F32_d8_d22_d31,
    637   },
    638   {
    639     ARRAY_SIZE(kInstruction_vcge_F32_d27_d3_d14),
    640     kInstruction_vcge_F32_d27_d3_d14,
    641   },
    642   {
    643     ARRAY_SIZE(kInstruction_vcge_F32_d11_d26_d6),
    644     kInstruction_vcge_F32_d11_d26_d6,
    645   },
    646   {
    647     ARRAY_SIZE(kInstruction_vcge_F32_d20_d24_d4),
    648     kInstruction_vcge_F32_d20_d24_d4,
    649   },
    650   {
    651     ARRAY_SIZE(kInstruction_vcge_F32_d1_d8_d3),
    652     kInstruction_vcge_F32_d1_d8_d3,
    653   },
    654   {
    655     ARRAY_SIZE(kInstruction_vcge_F32_d27_d17_d17),
    656     kInstruction_vcge_F32_d27_d17_d17,
    657   },
    658   {
    659     ARRAY_SIZE(kInstruction_vcge_F32_d25_d21_d8),
    660     kInstruction_vcge_F32_d25_d21_d8,
    661   },
    662   {
    663     ARRAY_SIZE(kInstruction_vcge_F32_d6_d0_d15),
    664     kInstruction_vcge_F32_d6_d0_d15,
    665   },
    666   {
    667     ARRAY_SIZE(kInstruction_vcge_F32_d4_d10_d9),
    668     kInstruction_vcge_F32_d4_d10_d9,
    669   },
    670   {
    671     ARRAY_SIZE(kInstruction_vcge_F32_d13_d26_d11),
    672     kInstruction_vcge_F32_d13_d26_d11,
    673   },
    674   {
    675     ARRAY_SIZE(kInstruction_vcge_F32_d7_d6_d18),
    676     kInstruction_vcge_F32_d7_d6_d18,
    677   },
    678   {
    679     ARRAY_SIZE(kInstruction_vcge_F32_d11_d7_d10),
    680     kInstruction_vcge_F32_d11_d7_d10,
    681   },
    682   {
    683     ARRAY_SIZE(kInstruction_vcge_F32_d17_d3_d10),
    684     kInstruction_vcge_F32_d17_d3_d10,
    685   },
    686   {
    687     ARRAY_SIZE(kInstruction_vcge_F32_d9_d19_d11),
    688     kInstruction_vcge_F32_d9_d19_d11,
    689   },
    690   {
    691     ARRAY_SIZE(kInstruction_vcge_F32_d9_d22_d10),
    692     kInstruction_vcge_F32_d9_d22_d10,
    693   },
    694   {
    695     ARRAY_SIZE(kInstruction_vcge_F32_d30_d0_d21),
    696     kInstruction_vcge_F32_d30_d0_d21,
    697   },
    698   {
    699     ARRAY_SIZE(kInstruction_vcge_F32_d13_d1_d15),
    700     kInstruction_vcge_F32_d13_d1_d15,
    701   },
    702   {
    703     ARRAY_SIZE(kInstruction_vcge_F32_d27_d11_d10),
    704     kInstruction_vcge_F32_d27_d11_d10,
    705   },
    706   {
    707     ARRAY_SIZE(kInstruction_vcge_F32_d7_d26_d9),
    708     kInstruction_vcge_F32_d7_d26_d9,
    709   },
    710   {
    711     ARRAY_SIZE(kInstruction_vcge_F32_d1_d12_d21),
    712     kInstruction_vcge_F32_d1_d12_d21,
    713   },
    714   {
    715     ARRAY_SIZE(kInstruction_vcge_F32_d26_d28_d30),
    716     kInstruction_vcge_F32_d26_d28_d30,
    717   },
    718   {
    719     ARRAY_SIZE(kInstruction_vcge_F32_d31_d14_d5),
    720     kInstruction_vcge_F32_d31_d14_d5,
    721   },
    722   {
    723     ARRAY_SIZE(kInstruction_vcge_F32_d29_d12_d7),
    724     kInstruction_vcge_F32_d29_d12_d7,
    725   },
    726   {
    727     ARRAY_SIZE(kInstruction_vcge_F32_d19_d30_d1),
    728     kInstruction_vcge_F32_d19_d30_d1,
    729   },
    730   {
    731     ARRAY_SIZE(kInstruction_vcge_F32_d4_d1_d26),
    732     kInstruction_vcge_F32_d4_d1_d26,
    733   },
    734   {
    735     ARRAY_SIZE(kInstruction_vcge_F32_d2_d13_d10),
    736     kInstruction_vcge_F32_d2_d13_d10,
    737   },
    738 };
    739 
    740 #endif  // VIXL_ASSEMBLER_COND_DT_DRT_DRD_DRN_DRM_FLOAT_F32_ONLY_VCGE_A32_H_
    741