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      1 // Copyright 2015, VIXL authors
      2 // All rights reserved.
      3 //
      4 // Redistribution and use in source and binary forms, with or without
      5 // modification, are permitted provided that the following conditions are met:
      6 //
      7 //   * Redistributions of source code must retain the above copyright notice,
      8 //     this list of conditions and the following disclaimer.
      9 //   * Redistributions in binary form must reproduce the above copyright notice,
     10 //     this list of conditions and the following disclaimer in the documentation
     11 //     and/or other materials provided with the distribution.
     12 //   * Neither the name of ARM Limited nor the names of its contributors may be
     13 //     used to endorse or promote products derived from this software without
     14 //     specific prior written permission.
     15 //
     16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
     17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
     20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
     23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26 
     27 
     28 // ---------------------------------------------------------------------
     29 // This file is auto generated using tools/generate_simulator_traces.py.
     30 //
     31 // PLEASE DO NOT EDIT.
     32 // ---------------------------------------------------------------------
     33 
     34 #ifndef VIXL_SIM_FRECPE_4H_TRACE_AARCH64_H_
     35 #define VIXL_SIM_FRECPE_4H_TRACE_AARCH64_H_
     36 
     37 const uint16_t kExpected_NEON_frecpe_4H[] = {
     38   0xff23, 0xfe00, 0xff23, 0xfe01,
     39   0xfe00, 0xff23, 0xfe01, 0xfc00,
     40   0xff23, 0xfe01, 0xfc00, 0xf400,
     41   0xfe01, 0xfc00, 0xf400, 0xfc00,
     42   0xfc00, 0xf400, 0xfc00, 0x7c00,
     43   0xf400, 0xfc00, 0x7c00, 0x73fc,
     44   0xfc00, 0x7c00, 0x73fc, 0x4000,
     45   0x7c00, 0x73fc, 0x4000, 0x3ffc,
     46   0x73fc, 0x4000, 0x3ffc, 0x3ffc,
     47   0x4000, 0x3ffc, 0x3ffc, 0x3c00,
     48   0x3ffc, 0x3ffc, 0x3c00, 0x3bfc,
     49   0x3ffc, 0x3c00, 0x3bfc, 0x3bfc,
     50   0x3c00, 0x3bfc, 0x3bfc, 0x3954,
     51   0x3bfc, 0x3bfc, 0x3954, 0x2e64,
     52   0x3bfc, 0x3954, 0x2e64, 0x0100,
     53   0x3954, 0x2e64, 0x0100, 0x0000,
     54   0x2e64, 0x0100, 0x0000, 0x7f23,
     55   0x0100, 0x0000, 0x7f23, 0x7e00,
     56   0x0000, 0x7f23, 0x7e00, 0x7f23,
     57   0x7f23, 0x7e00, 0x7f23, 0x7e01,
     58   0x7e00, 0x7f23, 0x7e01, 0x7c00,
     59   0x7f23, 0x7e01, 0x7c00, 0x7400,
     60   0x7e01, 0x7c00, 0x7400, 0x7c00,
     61   0x7c00, 0x7400, 0x7c00, 0xfc00,
     62   0x7400, 0x7c00, 0xfc00, 0xf3fc,
     63   0x7c00, 0xfc00, 0xf3fc, 0xc000,
     64   0xfc00, 0xf3fc, 0xc000, 0xbffc,
     65   0xf3fc, 0xc000, 0xbffc, 0xbffc,
     66   0xc000, 0xbffc, 0xbffc, 0xbc00,
     67   0xbffc, 0xbffc, 0xbc00, 0xbbfc,
     68   0xbffc, 0xbc00, 0xbbfc, 0xbbfc,
     69   0xbc00, 0xbbfc, 0xbbfc, 0xb954,
     70   0xbbfc, 0xbbfc, 0xb954, 0xae64,
     71   0xbbfc, 0xb954, 0xae64, 0x8100,
     72   0xb954, 0xae64, 0x8100, 0x8000,
     73   0xae64, 0x8100, 0x8000, 0xff23,
     74   0x8100, 0x8000, 0xff23, 0xfe00,
     75   0x8000, 0xff23, 0xfe00, 0xff23,
     76 };
     77 const unsigned kExpectedCount_NEON_frecpe_4H = 38;
     78 
     79 #endif  // VIXL_SIM_FRECPE_4H_TRACE_AARCH64_H_
     80