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      6 <title>move-result-wide</title>
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     11 
     12 <h1>move-result-wide</h1>
     13 
     14 <h2>Purpose</h2>
     15 
     16 <p>
     17 Move the double-word result of the most recent invoke-kind into the indicated
     18 register pair. This must be done as the instruction immediately after an
     19 invoke-kind whose (double-word) result is not to be ignored; anywhere else is
     20 invalid. 
     21 </p>
     22 
     23 <h2>Details</h2>
     24 
     25 <table class="instruc">
     26 <thead>
     27 <tr>
     28   <th>Op &amp; Format</th>
     29   <th>Mnemonic / Syntax</th>
     30   <th>Arguments</th>
     31 </tr>
     32 </thead>
     33 <tbody>
     34 <tr>
     35   <td>0b 11x</td>
     36   <td>move-result-wide vAA</td>
     37   <td><code>A:</code> destination register pair (8 bits)</td>
     38 </tr>
     39 </tbody>
     40 </table>
     41 
     42 <h2>Constraints</h2>
     43 
     44 <ul>
     45   <li>
     46     A+1 must be a valid register index in the current stack frame (which
     47     includes A itself being valid).
     48   </li>
     49   <li>
     50     The instruction must be immediately preceded (in the code array) by an
     51     invoke-kind instruction.
     52   </li>
     53   <li>
     54     The instruction must be immediately reached (in the actual control flow)
     55     through returning from this invoke-kind instruction (it must not be jumped
     56     to).
     57   </li>
     58   <li>
     59     The result delivered by the invoke-kind instruction must be either a long
     60     or a double value.
     61   </li>
     62 </ul>
     63  
     64 <h2>Behavior</h2>
     65 
     66 <ul>
     67   <li>
     68     The upper 32 bits of the result delivered by the invoke-kind instruction are
     69     moved to register vA, that is, vA' = result >> 0x20.
     70   </li>
     71   <li>
     72     The lower 32 bits of the result delivered by the invoke-kind instruction are
     73     moved to register v(A+1), that is, v(A+1)' = result & 0xffffffff.
     74   </li>
     75   <li>
     76     If register v(A-1) is the lower half of a register pair, register v(A-1)'
     77     becomes undefined.
     78   </li>
     79   <li>
     80     If register v(A+2) is the upper half of a register pair, register v(A+2)'
     81     becomes undefined.
     82   </li>
     83 </ul>
     84  
     85 <h2>Exceptions</h2>
     86 
     87 <p>
     88 None.
     89 </p>
     90 
     91 <h2>Notes</h2>
     92 
     93 <p>
     94 This instruction can also be thought of as reading the contents of a special
     95 "result" register that is made valid and defined by executing a non-void return
     96 instruction or a filled-new-array instruction. The execution of any other
     97 instruction (including this one) renders this special register invalid.
     98 </p>
     99 
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