1 %default {"result":"r0", "chkzero":"0"} 2 /* 3 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 4 * that specifies an instruction that performs "result = r0 op r1". 5 * This could be an ARM instruction or a function call. (If the result 6 * comes back in a register other than r0, you can override "result".) 7 * 8 * If "chkzero" is set to 1, we perform a divide-by-zero check on 9 * vCC (r1). Useful for integer division and modulus. 10 * 11 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 12 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 13 */ 14 /* binop/lit16 vA, vB, #+CCCC */ 15 FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 16 mov r2, rINST, lsr #12 @ r2<- B 17 ubfx r9, rINST, #8, #4 @ r9<- A 18 GET_VREG(r0, r2) @ r0<- vB 19 .if $chkzero 20 cmp r1, #0 @ is second operand zero? 21 beq common_errDivideByZero 22 .endif 23 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 24 25 $instr @ $result<- op, r0-r3 changed 26 GET_INST_OPCODE(ip) @ extract opcode from rINST 27 SET_VREG($result, r9) @ vAA<- $result 28 GOTO_OPCODE(ip) @ jump to next instruction 29 /* 10-13 instructions */ 30 31
