1 /* ------------------------------------------------------------------ 2 * Copyright (C) 1998-2009 PacketVideo 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either 13 * express or implied. 14 * See the License for the specific language governing permissions 15 * and limitations under the License. 16 * ------------------------------------------------------------------- 17 */ 18 /* 19 20 Pathname: fxp_mul32_c_equivalent.h 21 22 23 ------------------------------------------------------------------------------ 24 REVISION HISTORY 25 26 Who: Date: 27 Description: 28 ------------------------------------------------------------------------------ 29 INCLUDE DESCRIPTION 30 31 ------------------------------------------------------------------------------ 32 */ 33 34 #ifndef FXP_MUL32_ARM_V4 35 #define FXP_MUL32_ARM_V4 36 37 38 #ifdef __cplusplus 39 extern "C" 40 { 41 #endif 42 43 44 #include "pv_audio_type_defs.h" 45 46 47 #if defined(PV_ARM_V4) 48 49 #define preload_cache( a) 50 51 52 __inline Int32 shft_lft_1(Int32 L_var1) 53 { 54 Int32 x; 55 Int32 z = 1; /* rvct compiler problem */ 56 __asm 57 { 58 mov x, L_var1, asl 1 59 teq L_var1, x, asr z 60 eorne x, INT32_MAX, L_var1, asr #31 61 } 62 63 return(x); 64 } 65 66 67 __inline Int32 fxp_mul_16_by_16bb(Int32 L_var1, Int32 L_var2) 68 { 69 __asm 70 { 71 72 mov L_var2, L_var2, asl #16 73 mov L_var2, L_var2, asr #16 74 mov L_var1, L_var1, asl #16 75 mov L_var1, L_var1, asr #16 76 77 78 mul L_var1, L_var2, L_var1 79 } 80 81 return L_var1; 82 83 } 84 85 86 #define fxp_mul_16_by_16(a, b) fxp_mul_16_by_16bb( a, b) 87 88 89 __inline Int32 fxp_mul_16_by_16tb(Int32 L_var1, Int32 L_var2) 90 { 91 __asm 92 { 93 mov L_var2, L_var2, asl #16 94 mov L_var2, L_var2, asr #16 95 mov L_var1, L_var1, asr #16 96 97 mul L_var1, L_var2, L_var1 98 } 99 return L_var1; 100 } 101 102 __inline Int32 fxp_mul_16_by_16bt(Int32 L_var1, Int32 L_var2) 103 { 104 __asm 105 { 106 mov L_var2, L_var2, asr #16 107 mov L_var1, L_var1, asl #16 108 mov L_var1, L_var1, asr #16 109 110 mul L_var1, L_var2, L_var1 111 } 112 113 return L_var1; 114 115 } 116 117 118 __inline Int32 fxp_mul_16_by_16tt(Int32 L_var1, Int32 L_var2) 119 { 120 __asm 121 { 122 mov L_var2, L_var2, asr #16 123 mov L_var1, L_var1, asr #16 124 125 mul L_var1, L_var2, L_var1 126 } 127 128 return L_var1; 129 130 } 131 132 __inline Int32 fxp_mac_16_by_16(const Int32 L_var1, const Int32 L_var2, Int32 L_add) 133 { 134 __asm 135 { 136 mla L_add, L_var1, L_var2, L_add 137 } 138 return (L_add); 139 } 140 141 142 __inline Int32 fxp_mac_16_by_16_bb(const Int32 L_var1, Int32 L_var2, Int32 L_add) 143 { 144 __asm 145 { 146 mov L_var2, L_var2, asl #16 147 mov L_var2, L_var2, asr #16 148 mla L_add, L_var1, L_var2, L_add 149 } 150 return L_add; 151 } 152 153 __inline Int32 fxp_mac_16_by_16_bt(Int16 L_var1, Int32 L_var2, Int32 L_add) 154 { 155 __asm 156 { 157 mov L_var2, L_var2, asr #16 158 mla L_add, L_var1, L_var2, L_add 159 } 160 return L_add; 161 } 162 163 164 __inline Int32 cmplx_mul32_by_16(Int32 x, const Int32 y, Int32 exp_jw) 165 { 166 167 Int32 result64_hi; 168 Int32 rTmp0; 169 Int32 iTmp0; 170 __asm 171 { 172 mov rTmp0, exp_jw, asr #16 173 mov rTmp0, rTmp0, asl #16 174 mov iTmp0, exp_jw, asl #16 175 smull rTmp0, result64_hi, x, rTmp0 176 smlal iTmp0, result64_hi, y, iTmp0 177 } 178 179 return (result64_hi); 180 } 181 182 183 __inline Int32 fxp_mul32_by_16(Int32 L_var1, Int32 L_var2) 184 { 185 Int32 result64_hi; 186 __asm 187 { 188 mov L_var2, L_var2, asl #16 189 smull L_var1, result64_hi, L_var2, L_var1 190 } 191 return (result64_hi); 192 } 193 194 195 196 #define fxp_mul32_by_16b( a, b) fxp_mul32_by_16( a, b) 197 198 199 200 __inline Int32 fxp_mul32_by_16t(Int32 L_var1, Int32 L_var2) 201 { 202 203 Int32 result64_hi; 204 __asm 205 { 206 mov L_var2, L_var2, asr #16 207 mov L_var2, L_var2, asl #16 208 smull L_var1, result64_hi, L_var2, L_var1 209 } 210 return (result64_hi); 211 212 } 213 214 __inline Int32 fxp_mac32_by_16(Int32 L_var1, Int32 L_var2, Int32 L_add) 215 { 216 217 __asm 218 { 219 mov L_var2, L_var2, asl #16 220 smlal L_var1, L_add, L_var2, L_var1 221 } 222 223 return (L_add); 224 } 225 226 227 __inline int64 fxp_mac64_Q31(int64 sum, const Int32 L_var1, const Int32 L_var2) 228 { 229 uint32 b = (UInt32)(sum); 230 int32 c = Int32(sum >> 32); 231 __asm 232 { 233 smlal b, c, L_var1, L_var2 234 } 235 return (((int64(c)) << 32) | b); 236 } 237 238 239 __inline Int32 fxp_mul32_Q31(Int32 L_var1, const Int32 L_var2) 240 { 241 Int32 result64_hi; 242 __asm 243 { 244 smull L_var1, result64_hi, L_var2, L_var1 245 } 246 return (result64_hi); 247 } 248 249 250 __inline Int32 fxp_mac32_Q31(Int32 L_add, Int32 L_var1, const Int32 L_var2) 251 { 252 __asm 253 { 254 smlal L_var1, L_add, L_var2, L_var1 255 } 256 return L_add; 257 } 258 259 __inline Int32 fxp_msu32_Q31(Int32 L_sub, Int32 L_var1, const Int32 L_var2) 260 { 261 __asm 262 { 263 rsb L_var1, L_var1, #0 264 smlal L_var1, L_sub, L_var2, L_var1 265 } 266 return L_sub; 267 } 268 269 270 __inline Int32 fxp_mul32_Q30(const Int32 L_var1, const Int32 L_var2) 271 { 272 Int32 result64_hi; 273 Int32 result64_lo; 274 __asm 275 { 276 smull result64_lo, result64_hi, L_var2, L_var1 277 mov result64_hi, result64_hi, asl #2 278 orr result64_hi, result64_hi, result64_lo, lsr #30 279 } 280 return (result64_hi); 281 } 282 283 284 __inline Int32 fxp_mac32_Q30(const Int32 L_var1, const Int32 L_var2, Int32 L_add) 285 { 286 Int32 result64_hi; 287 Int32 result64_lo; 288 __asm 289 { 290 smull result64_lo, result64_hi, L_var2, L_var1 291 add L_add, L_add, result64_hi, asl #2 292 add L_add, L_add, result64_lo, lsr #30 293 } 294 return (L_add); 295 } 296 297 298 __inline Int32 fxp_mul32_Q29(const Int32 L_var1, const Int32 L_var2) 299 { 300 Int32 result64_hi; 301 Int32 result64_lo; 302 __asm 303 { 304 smull result64_lo, result64_hi, L_var2, L_var1 305 mov result64_hi, result64_hi, asl #3 306 orr result64_hi, result64_hi, result64_lo, lsr #29 307 } 308 return (result64_hi); 309 } 310 311 __inline Int32 fxp_mac32_Q29(const Int32 L_var1, const Int32 L_var2, Int32 L_add) 312 { 313 Int32 result64_hi; 314 Int32 result64_lo; 315 __asm 316 { 317 smull result64_lo, result64_hi, L_var2, L_var1 318 add L_add, L_add, result64_hi, asl #3 319 add L_add, L_add, result64_lo, lsr #29 320 } 321 return (L_add); 322 } 323 324 __inline Int32 fxp_msu32_Q29(const Int32 L_var1, const Int32 L_var2, Int32 L_sub) 325 { 326 Int32 result64_hi; 327 Int32 result64_lo; 328 __asm 329 { 330 smull result64_lo, result64_hi, L_var2, L_var1 331 sub L_sub, L_sub, result64_hi, asl #3 332 sub L_sub, L_sub, result64_lo, lsr #29 333 } 334 return (L_sub); 335 } 336 337 __inline Int32 fxp_mul32_Q28(const Int32 L_var1, const Int32 L_var2) 338 { 339 Int32 result64_hi; 340 Int32 result64_lo; 341 __asm 342 { 343 smull result64_lo, result64_hi, L_var2, L_var1 344 mov result64_hi, result64_hi, asl #4 345 orr result64_hi, result64_hi, result64_lo, lsr #28 346 } 347 return (result64_hi); 348 } 349 350 __inline Int32 fxp_mul32_Q27(const Int32 L_var1, const Int32 L_var2) 351 { 352 Int32 result64_hi; 353 Int32 result64_lo; 354 __asm 355 { 356 smull result64_lo, result64_hi, L_var2, L_var1 357 mov result64_hi, result64_hi, asl #5 358 orr result64_hi, result64_hi, result64_lo, lsr #27 359 } 360 return (result64_hi); 361 } 362 363 __inline Int32 fxp_mul32_Q26(const Int32 L_var1, const Int32 L_var2) 364 { 365 Int32 result64_hi; 366 Int32 result64_lo; 367 __asm 368 { 369 smull result64_lo, result64_hi, L_var2, L_var1 370 mov result64_hi, result64_hi, asl #6 371 orr result64_hi, result64_hi, result64_lo, lsr #26 372 } 373 return (result64_hi); 374 } 375 376 __inline Int32 fxp_mul32_Q20(const Int32 L_var1, const Int32 L_var2) 377 { 378 Int32 result64_hi; 379 Int32 result64_lo; 380 __asm 381 { 382 smull result64_lo, result64_hi, L_var2, L_var1 383 mov result64_hi, result64_hi, asl #12 384 orr result64_hi, result64_hi, result64_lo, lsr #20 385 } 386 return (result64_hi); 387 } 388 389 __inline Int32 fxp_mul32_Q15(const Int32 L_var1, const Int32 L_var2) 390 { 391 Int32 result64_hi; 392 Int32 result64_lo; 393 __asm 394 { 395 smull result64_lo, result64_hi, L_var2, L_var1 396 mov result64_hi, result64_hi, asl #17 397 orr result64_hi, result64_hi, result64_lo, lsr #15 398 } 399 return (result64_hi); 400 } 401 402 403 404 405 __inline Int32 fxp_mul32_Q14(const Int32 L_var1, const Int32 L_var2) 406 { 407 Int32 result64_hi; 408 Int32 result64_lo; 409 __asm 410 { 411 smull result64_lo, result64_hi, L_var2, L_var1 412 mov result64_hi, result64_hi, asl #18 413 orr result64_hi, result64_hi, result64_lo, lsr #14 414 } 415 return (result64_hi); 416 } 417 418 419 420 #endif 421 422 423 #ifdef __cplusplus 424 } 425 #endif 426 427 428 #endif /* FXP_MUL32 */ 429 430
