1 /* 2 * Copyright (C) 2008 Apple Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY 14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR 17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #ifndef MacroAssembler_h 27 #define MacroAssembler_h 28 29 #include <wtf/Platform.h> 30 31 #if ENABLE(ASSEMBLER) 32 33 #if CPU(ARM_THUMB2) 34 #include "MacroAssemblerARMv7.h" 35 namespace JSC { typedef MacroAssemblerARMv7 MacroAssemblerBase; }; 36 37 #elif CPU(ARM_TRADITIONAL) 38 #include "MacroAssemblerARM.h" 39 namespace JSC { typedef MacroAssemblerARM MacroAssemblerBase; }; 40 41 #elif CPU(X86) 42 #include "MacroAssemblerX86.h" 43 namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; }; 44 45 #elif CPU(X86_64) 46 #include "MacroAssemblerX86_64.h" 47 namespace JSC { typedef MacroAssemblerX86_64 MacroAssemblerBase; }; 48 49 #else 50 #error "The MacroAssembler is not supported on this platform." 51 #endif 52 53 54 namespace JSC { 55 56 class MacroAssembler : public MacroAssemblerBase { 57 public: 58 59 using MacroAssemblerBase::pop; 60 using MacroAssemblerBase::jump; 61 using MacroAssemblerBase::branch32; 62 using MacroAssemblerBase::branch16; 63 #if CPU(X86_64) 64 using MacroAssemblerBase::branchPtr; 65 using MacroAssemblerBase::branchTestPtr; 66 #endif 67 68 69 // Platform agnostic onvenience functions, 70 // described in terms of other macro assembly methods. 71 void pop() 72 { 73 addPtr(Imm32(sizeof(void*)), stackPointerRegister); 74 } 75 76 void peek(RegisterID dest, int index = 0) 77 { 78 loadPtr(Address(stackPointerRegister, (index * sizeof(void*))), dest); 79 } 80 81 void poke(RegisterID src, int index = 0) 82 { 83 storePtr(src, Address(stackPointerRegister, (index * sizeof(void*)))); 84 } 85 86 void poke(Imm32 value, int index = 0) 87 { 88 store32(value, Address(stackPointerRegister, (index * sizeof(void*)))); 89 } 90 91 void poke(ImmPtr imm, int index = 0) 92 { 93 storePtr(imm, Address(stackPointerRegister, (index * sizeof(void*)))); 94 } 95 96 97 // Backwards banches, these are currently all implemented using existing forwards branch mechanisms. 98 void branchPtr(Condition cond, RegisterID op1, ImmPtr imm, Label target) 99 { 100 branchPtr(cond, op1, imm).linkTo(target, this); 101 } 102 103 void branch32(Condition cond, RegisterID op1, RegisterID op2, Label target) 104 { 105 branch32(cond, op1, op2).linkTo(target, this); 106 } 107 108 void branch32(Condition cond, RegisterID op1, Imm32 imm, Label target) 109 { 110 branch32(cond, op1, imm).linkTo(target, this); 111 } 112 113 void branch32(Condition cond, RegisterID left, Address right, Label target) 114 { 115 branch32(cond, left, right).linkTo(target, this); 116 } 117 118 void branch16(Condition cond, BaseIndex left, RegisterID right, Label target) 119 { 120 branch16(cond, left, right).linkTo(target, this); 121 } 122 123 void branchTestPtr(Condition cond, RegisterID reg, Label target) 124 { 125 branchTestPtr(cond, reg).linkTo(target, this); 126 } 127 128 void jump(Label target) 129 { 130 jump().linkTo(target, this); 131 } 132 133 134 // Ptr methods 135 // On 32-bit platforms (i.e. x86), these methods directly map onto their 32-bit equivalents. 136 // FIXME: should this use a test for 32-bitness instead of this specific exception? 137 #if !CPU(X86_64) 138 void addPtr(RegisterID src, RegisterID dest) 139 { 140 add32(src, dest); 141 } 142 143 void addPtr(Imm32 imm, RegisterID srcDest) 144 { 145 add32(imm, srcDest); 146 } 147 148 void addPtr(ImmPtr imm, RegisterID dest) 149 { 150 add32(Imm32(imm), dest); 151 } 152 153 void addPtr(Imm32 imm, RegisterID src, RegisterID dest) 154 { 155 add32(imm, src, dest); 156 } 157 158 void andPtr(RegisterID src, RegisterID dest) 159 { 160 and32(src, dest); 161 } 162 163 void andPtr(Imm32 imm, RegisterID srcDest) 164 { 165 and32(imm, srcDest); 166 } 167 168 void orPtr(RegisterID src, RegisterID dest) 169 { 170 or32(src, dest); 171 } 172 173 void orPtr(ImmPtr imm, RegisterID dest) 174 { 175 or32(Imm32(imm), dest); 176 } 177 178 void orPtr(Imm32 imm, RegisterID dest) 179 { 180 or32(imm, dest); 181 } 182 183 void subPtr(RegisterID src, RegisterID dest) 184 { 185 sub32(src, dest); 186 } 187 188 void subPtr(Imm32 imm, RegisterID dest) 189 { 190 sub32(imm, dest); 191 } 192 193 void subPtr(ImmPtr imm, RegisterID dest) 194 { 195 sub32(Imm32(imm), dest); 196 } 197 198 void xorPtr(RegisterID src, RegisterID dest) 199 { 200 xor32(src, dest); 201 } 202 203 void xorPtr(Imm32 imm, RegisterID srcDest) 204 { 205 xor32(imm, srcDest); 206 } 207 208 209 void loadPtr(ImplicitAddress address, RegisterID dest) 210 { 211 load32(address, dest); 212 } 213 214 void loadPtr(BaseIndex address, RegisterID dest) 215 { 216 load32(address, dest); 217 } 218 219 void loadPtr(void* address, RegisterID dest) 220 { 221 load32(address, dest); 222 } 223 224 DataLabel32 loadPtrWithAddressOffsetPatch(Address address, RegisterID dest) 225 { 226 return load32WithAddressOffsetPatch(address, dest); 227 } 228 229 void setPtr(Condition cond, RegisterID left, Imm32 right, RegisterID dest) 230 { 231 set32(cond, left, right, dest); 232 } 233 234 void storePtr(RegisterID src, ImplicitAddress address) 235 { 236 store32(src, address); 237 } 238 239 void storePtr(RegisterID src, BaseIndex address) 240 { 241 store32(src, address); 242 } 243 244 void storePtr(RegisterID src, void* address) 245 { 246 store32(src, address); 247 } 248 249 void storePtr(ImmPtr imm, ImplicitAddress address) 250 { 251 store32(Imm32(imm), address); 252 } 253 254 void storePtr(ImmPtr imm, void* address) 255 { 256 store32(Imm32(imm), address); 257 } 258 259 DataLabel32 storePtrWithAddressOffsetPatch(RegisterID src, Address address) 260 { 261 return store32WithAddressOffsetPatch(src, address); 262 } 263 264 265 Jump branchPtr(Condition cond, RegisterID left, RegisterID right) 266 { 267 return branch32(cond, left, right); 268 } 269 270 Jump branchPtr(Condition cond, RegisterID left, ImmPtr right) 271 { 272 return branch32(cond, left, Imm32(right)); 273 } 274 275 Jump branchPtr(Condition cond, RegisterID left, Address right) 276 { 277 return branch32(cond, left, right); 278 } 279 280 Jump branchPtr(Condition cond, Address left, RegisterID right) 281 { 282 return branch32(cond, left, right); 283 } 284 285 Jump branchPtr(Condition cond, AbsoluteAddress left, RegisterID right) 286 { 287 return branch32(cond, left, right); 288 } 289 290 Jump branchPtr(Condition cond, Address left, ImmPtr right) 291 { 292 return branch32(cond, left, Imm32(right)); 293 } 294 295 Jump branchPtr(Condition cond, AbsoluteAddress left, ImmPtr right) 296 { 297 return branch32(cond, left, Imm32(right)); 298 } 299 300 Jump branchTestPtr(Condition cond, RegisterID reg, RegisterID mask) 301 { 302 return branchTest32(cond, reg, mask); 303 } 304 305 Jump branchTestPtr(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1)) 306 { 307 return branchTest32(cond, reg, mask); 308 } 309 310 Jump branchTestPtr(Condition cond, Address address, Imm32 mask = Imm32(-1)) 311 { 312 return branchTest32(cond, address, mask); 313 } 314 315 Jump branchTestPtr(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1)) 316 { 317 return branchTest32(cond, address, mask); 318 } 319 320 321 Jump branchAddPtr(Condition cond, RegisterID src, RegisterID dest) 322 { 323 return branchAdd32(cond, src, dest); 324 } 325 326 Jump branchSubPtr(Condition cond, Imm32 imm, RegisterID dest) 327 { 328 return branchSub32(cond, imm, dest); 329 } 330 #endif 331 332 }; 333 334 } // namespace JSC 335 336 #endif // ENABLE(ASSEMBLER) 337 338 #endif // MacroAssembler_h 339