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    Searched defs:Operand (Results 1 - 11 of 11) sorted by null

  /external/v8/src/mips/
assembler-mips-inl.h 56 // Operand and MemOperand
58 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
64 Operand::Operand(const ExternalReference& f) {
70 Operand::Operand(const char* s) {
76 Operand::Operand(Smi* value) {
82 Operand::Operand(Register rm)
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assembler-mips.cc 203 // Implementation of Operand and MemOperand.
206 Operand::Operand(Handle<Object> handle) {
221 MemOperand::MemOperand(Register rm, int16_t offset) : Operand(rm) {
  /external/v8/src/arm/
assembler-arm-inl.h 156 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
163 Operand::Operand(const char* s) {
170 Operand::Operand(const ExternalReference& f) {
177 Operand::Operand(Smi* value) {
184 Operand::Operand(Register rm)
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assembler-thumb2-inl.h 156 Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) {
163 Operand::Operand(const char* s) {
170 Operand::Operand(const ExternalReference& f) {
177 Operand::Operand(Smi* value) {
184 Operand::Operand(Register rm)
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assembler-arm.cc 225 // Implementation of Operand and MemOperand
228 Operand::Operand(Handle<Object> handle) {
244 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
260 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
311 I = 1 << 25, // immediate shifter operand (or not)
655 const Operand& x) {
664 // The immediate operand cannot be encoded as a shifter operand, so loa
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assembler-thumb2.cc 205 // Implementation of Operand and MemOperand
208 Operand::Operand(Handle<Object> handle) {
224 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
240 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
291 I = 1 << 25, // immediate shifter operand (or not)
635 const Operand& x) {
644 // The immediate operand cannot be encoded as a shifter operand, so loa
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  /external/v8/src/ia32/
assembler-ia32-inl.h 280 void Operand::set_modrm(int mod, Register rm) {
287 void Operand::set_sib(ScaleFactor scale, Register index, Register base) {
297 void Operand::set_disp8(int8_t disp) {
303 void Operand::set_dispr(int32_t disp, RelocInfo::Mode rmode) {
311 Operand::Operand(Register reg) {
317 Operand::Operand(int32_t disp, RelocInfo::Mode rmode) {
assembler-ia32.cc 73 __ mov(ebp, Operand(esp));
78 __ mov(edx, Operand(eax));
84 __ xor_(eax, Operand(edx)); // Different if CPUID is supported.
88 __ xor_(eax, Operand(eax));
89 __ xor_(edx, Operand(edx));
105 __ mov(eax, Operand(edx));
107 __ mov(edx, Operand(ecx));
111 __ mov(esp, Operand(ebp));
205 // Implementation of Operand
207 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode)
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  /dalvik/dx/src/com/android/dx/ssa/
PhiInsn.java 44 private final ArrayList<Operand> operands = new ArrayList<Operand>();
69 * operand and will be derived later.
90 for (Operand o : operands) {
122 * Adds an operand to this phi instruction.
124 * @param registerSpec register spec, including type and reg of operand
125 * @param predBlock predecessor block to be associated with this operand
129 operands.add(new Operand(registerSpec, predBlock.getIndex(),
178 * Gets sources. Constructed lazily from phi operand data structures and
189 // How'd this happen? A phi insn with no operand
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  /external/v8/src/x64/
assembler-x64.cc 185 // Implementation of Operand
187 Operand::Operand(Register base, int32_t disp) : rex_(0) {
206 Operand::Operand(Register base,
227 Operand::Operand(Register index,
430 void Assembler::emit_operand(int code, const Operand& adr) {
439 // Emit the rest of the encoded operand.
447 void Assembler::arithmetic_op(byte opcode, Register reg, const Operand& op)
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  /prebuilt/sdk/tools/lib/
dx.jar 

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