| /dalvik/vm/compiler/template/armv5te/ |
| header.S | 65 r7 rINST first 16-bit code unit of current instruction
77 #define rINST r7
|
| /dalvik/vm/mterp/x86-atom/ |
| header.S | 46 * %ebx rINST first 16-bit code unit of current instruction
62 #define rINST %ebx
144 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
148 movzwl (rPC), rINST
162 movzwl (rPC), rINST
173 movzwl (rPC), rINST
271 movzbl 1(rPC), rINST
286 movzbl (\_count*2 + 1)(rPC), rINST
292 movzbl 1(rPC), rINST
310 movzbl 1(rPC), rINST
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| header.S | 60 r7 rINST first 16-bit code unit of current instruction
72 #define rINST r7
104 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
106 #define FETCH_INST() ldrh rINST, [rPC]
120 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
124 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
134 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
139 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
160 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
|
| /dalvik/vm/compiler/template/out/ |
| CompilerTemplateAsm-armv5te-vfp.S | 72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7
[all...] |
| CompilerTemplateAsm-armv5te.S | 72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7
[all...] |
| CompilerTemplateAsm-armv7-a-neon.S | 72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7
[all...] |
| CompilerTemplateAsm-armv7-a.S | 72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7
[all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-x86-atom.S | 53 * %ebx rINST first 16-bit code unit of current instruction
69 #define rINST %ebx
151 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
155 movzwl (rPC), rINST
169 movzwl (rPC), rINST
180 movzwl (rPC), rINST
278 movzbl 1(rPC), rINST
293 movzbl (\_count*2 + 1)(rPC), rINST
299 movzbl 1(rPC), rINST
317 movzbl 1(rPC), rINST
[all...] |
| InterpAsm-x86.S | 65 rINST bx first 16-bit code of current instruction
71 o rPC, rFP, rIBASE, rINST/rOPCODE valid on handler entry and exit
72 o eax and ecx are scratch, rINST/ebx sometimes scratch
82 #define rINST %bx
152 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
157 * Fetch the nth instruction word from rPC into rINST. Does not advance
169 * Extract the opcode of the instruction in rINST
184 * Note: assumes opcode previously fetched and in rINST, and
253 movw 2(rPC),rINST # rINST <= BBB
[all...] |
| InterpAsm-armv4t.S | 67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
348 FETCH_INST() @ load rINST from rP
[all...] |
| InterpAsm-armv5te-vfp.S | 67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
348 FETCH_INST() @ load rINST from rP
[all...] |
| InterpAsm-armv5te.S | 67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
348 FETCH_INST() @ load rINST from rP
[all...] |
| InterpAsm-armv7-a-neon.S | 67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
358 FETCH_INST() @ load rINST from rP
[all...] |
| InterpAsm-armv7-a.S | 67 r7 rINST first 16-bit code unit of current instruction
79 #define rINST r7
111 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
113 #define FETCH_INST() ldrh rINST, [rPC]
127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
131 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
141 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
358 FETCH_INST() @ load rINST from rP
[all...] |
| /dalvik/vm/mterp/x86/ |
| header.S | 58 rINST bx first 16-bit code of current instruction
64 o rPC, rFP, rIBASE, rINST/rOPCODE valid on handler entry and exit
65 o eax and ecx are scratch, rINST/ebx sometimes scratch
75 #define rINST %bx
145 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
150 * Fetch the nth instruction word from rPC into rINST. Does not advance
162 * Extract the opcode of the instruction in rINST
177 * Note: assumes opcode previously fetched and in rINST, and
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