| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 115 int Rd, int Rn,
120 int Rd, int Rm, int Rs, int Rn) = 0;
135 virtual void BX(int cc, int Rn) = 0;
146 int Rn, uint32_t offset = immed12_pre(0)) = 0;
148 int Rn, uint32_t offset = immed12_pre(0)) = 0;
150 int Rn, uint32_t offset = immed12_pre(0)) = 0;
152 int Rn, uint32_t offset = immed12_pre(0)) = 0;
155 int Rn, uint32_t offset = immed8_pre(0)) = 0;
157 int Rn, uint32_t offset = immed8_pre(0)) = 0;
159 int Rn, uint32_t offset = immed8_pre(0)) = 0
[all...] |
| ARMAssembler.h | 61 int Rd, int Rn,
64 int Rd, int Rm, int Rs, int Rn);
78 virtual void BX(int cc, int Rn);
86 int Rn, uint32_t offset = immed12_pre(0));
88 int Rn, uint32_t offset = immed12_pre(0));
90 int Rn, uint32_t offset = immed12_pre(0));
92 int Rn, uint32_t offset = immed12_pre(0));
94 int Rn, uint32_t offset = immed8_pre(0));
96 int Rn, uint32_t offset = immed8_pre(0));
98 int Rn, uint32_t offset = immed8_pre(0))
[all...] |
| ARMAssemblerProxy.h | 51 int Rd, int Rn,
54 int Rd, int Rm, int Rs, int Rn);
68 virtual void BX(int cc, int Rn);
76 int Rn, uint32_t offset = immed12_pre(0));
78 int Rn, uint32_t offset = immed12_pre(0));
80 int Rn, uint32_t offset = immed12_pre(0));
82 int Rn, uint32_t offset = immed12_pre(0));
84 int Rn, uint32_t offset = immed8_pre(0));
86 int Rn, uint32_t offset = immed8_pre(0));
88 int Rn, uint32_t offset = immed8_pre(0))
[all...] |
| ARMAssemblerProxy.cpp | 70 int Rd, int Rn, uint32_t Op2)
72 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
75 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
76 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
104 void ARMAssemblerProxy::BX(int cc, int Rn) {
105 mTarget->BX(cc, Rn);
121 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
122 mTarget->LDR(cc, Rd, Rn, offset);
124 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
125 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| ARMAssembler.cpp | 212 int s, int Rd, int Rn, uint32_t Op2)
214 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
224 int Rd, int Rm, int Rs, int Rn) {
226 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
228 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
283 void ARMAssembler::BX(int cc, int Rn)
285 *mPC++ = (cc<<28) | 0x12FFF10 | Rn;
294 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) {
295 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset;
297 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset)
[all...] |
| /external/qemu/ |
| trace.c | 799 int Rn = (insn >> 12) & 15;
802 result += _interlock_use(Rn);
804 if (Rn != 0) /* UNDEFINED */
837 int Rn = (insn >> 16) & 15;
839 result += _interlock_use(Rn) + _interlock_use(Rm);
846 int Rn = (insn >> 16) & 15;
848 result += _interlock_use(Rn);
860 int Rn = (insn >> 16) & 15;
862 result += _interlock_use(Rn) + _interlock_use(Rm);
873 int Rn = (insn >> 16) & 15
[all...] |
| arm-dis.c | 1744 int rn = (given >> 16) & 0xf; local
2073 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
2286 int rn = ((given >> 16) & 0xf); local
2316 int rn = ((given >> 16) & 0xf); local
2391 int rn = ((given >> 16) & 0xf); local
[all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 295 if (format[1] == 'n') { // 'rn: Rn register
585 // Rn field to encode it.
586 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
589 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
590 // Rn field to encode the Rd register and the Rd field to encode
591 // the Rn register.
592 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
596 // when referring to the target registers. They are mapped to the Rn
599 // RdHi == Rn fiel
[all...] |
