1 /* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 1999-2010, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * $Id: sbhnddma.h,v 13.11.250.5.16.1 2009/07/21 14:04:51 Exp $ 26 */ 27 28 29 #ifndef _sbhnddma_h_ 30 #define _sbhnddma_h_ 31 32 33 34 35 36 37 38 typedef volatile struct { 39 uint32 control; 40 uint32 addr; 41 uint32 ptr; 42 uint32 status; 43 } dma32regs_t; 44 45 typedef volatile struct { 46 dma32regs_t xmt; 47 dma32regs_t rcv; 48 } dma32regp_t; 49 50 typedef volatile struct { 51 uint32 fifoaddr; 52 uint32 fifodatalow; 53 uint32 fifodatahigh; 54 uint32 pad; 55 } dma32diag_t; 56 57 58 typedef volatile struct { 59 uint32 ctrl; 60 uint32 addr; 61 } dma32dd_t; 62 63 64 #define D32RINGALIGN_BITS 12 65 #define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 66 #define D32RINGALIGN (1 << D32RINGALIGN_BITS) 67 #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 68 69 70 #define XC_XE ((uint32)1 << 0) 71 #define XC_SE ((uint32)1 << 1) 72 #define XC_LE ((uint32)1 << 2) 73 #define XC_FL ((uint32)1 << 4) 74 #define XC_PD ((uint32)1 << 11) 75 #define XC_AE ((uint32)3 << 16) 76 #define XC_AE_SHIFT 16 77 78 79 #define XP_LD_MASK 0xfff 80 81 82 #define XS_CD_MASK 0x0fff 83 #define XS_XS_MASK 0xf000 84 #define XS_XS_SHIFT 12 85 #define XS_XS_DISABLED 0x0000 86 #define XS_XS_ACTIVE 0x1000 87 #define XS_XS_IDLE 0x2000 88 #define XS_XS_STOPPED 0x3000 89 #define XS_XS_SUSP 0x4000 90 #define XS_XE_MASK 0xf0000 91 #define XS_XE_SHIFT 16 92 #define XS_XE_NOERR 0x00000 93 #define XS_XE_DPE 0x10000 94 #define XS_XE_DFU 0x20000 95 #define XS_XE_BEBR 0x30000 96 #define XS_XE_BEDA 0x40000 97 #define XS_AD_MASK 0xfff00000 98 #define XS_AD_SHIFT 20 99 100 101 #define RC_RE ((uint32)1 << 0) 102 #define RC_RO_MASK 0xfe 103 #define RC_RO_SHIFT 1 104 #define RC_FM ((uint32)1 << 8) 105 #define RC_SH ((uint32)1 << 9) 106 #define RC_OC ((uint32)1 << 10) 107 #define RC_PD ((uint32)1 << 11) 108 #define RC_AE ((uint32)3 << 16) 109 #define RC_AE_SHIFT 16 110 111 112 #define RP_LD_MASK 0xfff 113 114 115 #define RS_CD_MASK 0x0fff 116 #define RS_RS_MASK 0xf000 117 #define RS_RS_SHIFT 12 118 #define RS_RS_DISABLED 0x0000 119 #define RS_RS_ACTIVE 0x1000 120 #define RS_RS_IDLE 0x2000 121 #define RS_RS_STOPPED 0x3000 122 #define RS_RE_MASK 0xf0000 123 #define RS_RE_SHIFT 16 124 #define RS_RE_NOERR 0x00000 125 #define RS_RE_DPE 0x10000 126 #define RS_RE_DFO 0x20000 127 #define RS_RE_BEBW 0x30000 128 #define RS_RE_BEDA 0x40000 129 #define RS_AD_MASK 0xfff00000 130 #define RS_AD_SHIFT 20 131 132 133 #define FA_OFF_MASK 0xffff 134 #define FA_SEL_MASK 0xf0000 135 #define FA_SEL_SHIFT 16 136 #define FA_SEL_XDD 0x00000 137 #define FA_SEL_XDP 0x10000 138 #define FA_SEL_RDD 0x40000 139 #define FA_SEL_RDP 0x50000 140 #define FA_SEL_XFD 0x80000 141 #define FA_SEL_XFP 0x90000 142 #define FA_SEL_RFD 0xc0000 143 #define FA_SEL_RFP 0xd0000 144 #define FA_SEL_RSD 0xe0000 145 #define FA_SEL_RSP 0xf0000 146 147 148 #define CTRL_BC_MASK 0x1fff 149 #define CTRL_AE ((uint32)3 << 16) 150 #define CTRL_AE_SHIFT 16 151 #define CTRL_EOT ((uint32)1 << 28) 152 #define CTRL_IOC ((uint32)1 << 29) 153 #define CTRL_EOF ((uint32)1 << 30) 154 #define CTRL_SOF ((uint32)1 << 31) 155 156 157 #define CTRL_CORE_MASK 0x0ff00000 158 159 160 161 162 typedef volatile struct { 163 uint32 control; 164 uint32 ptr; 165 uint32 addrlow; 166 uint32 addrhigh; 167 uint32 status0; 168 uint32 status1; 169 } dma64regs_t; 170 171 typedef volatile struct { 172 dma64regs_t tx; 173 dma64regs_t rx; 174 } dma64regp_t; 175 176 typedef volatile struct { 177 uint32 fifoaddr; 178 uint32 fifodatalow; 179 uint32 fifodatahigh; 180 uint32 pad; 181 } dma64diag_t; 182 183 184 typedef volatile struct { 185 uint32 ctrl1; 186 uint32 ctrl2; 187 uint32 addrlow; 188 uint32 addrhigh; 189 } dma64dd_t; 190 191 192 #define D64RINGALIGN_BITS 13 193 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 194 #define D64RINGALIGN (1 << D64RINGALIGN_BITS) 195 #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 196 197 198 #define D64_XC_XE 0x00000001 199 #define D64_XC_SE 0x00000002 200 #define D64_XC_LE 0x00000004 201 #define D64_XC_FL 0x00000010 202 #define D64_XC_PD 0x00000800 203 #define D64_XC_AE 0x00030000 204 #define D64_XC_AE_SHIFT 16 205 206 207 #define D64_XP_LD_MASK 0x00000fff 208 209 210 #define D64_XS0_CD_MASK 0x00001fff 211 #define D64_XS0_XS_MASK 0xf0000000 212 #define D64_XS0_XS_SHIFT 28 213 #define D64_XS0_XS_DISABLED 0x00000000 214 #define D64_XS0_XS_ACTIVE 0x10000000 215 #define D64_XS0_XS_IDLE 0x20000000 216 #define D64_XS0_XS_STOPPED 0x30000000 217 #define D64_XS0_XS_SUSP 0x40000000 218 219 #define D64_XS1_AD_MASK 0x0001ffff 220 #define D64_XS1_XE_MASK 0xf0000000 221 #define D64_XS1_XE_SHIFT 28 222 #define D64_XS1_XE_NOERR 0x00000000 223 #define D64_XS1_XE_DPE 0x10000000 224 #define D64_XS1_XE_DFU 0x20000000 225 #define D64_XS1_XE_DTE 0x30000000 226 #define D64_XS1_XE_DESRE 0x40000000 227 #define D64_XS1_XE_COREE 0x50000000 228 229 230 #define D64_RC_RE 0x00000001 231 #define D64_RC_RO_MASK 0x000000fe 232 #define D64_RC_RO_SHIFT 1 233 #define D64_RC_FM 0x00000100 234 #define D64_RC_SH 0x00000200 235 #define D64_RC_OC 0x00000400 236 #define D64_RC_PD 0x00000800 237 #define D64_RC_AE 0x00030000 238 #define D64_RC_AE_SHIFT 16 239 240 241 #define D64_RP_LD_MASK 0x00000fff 242 243 244 #define D64_RS0_CD_MASK 0x00001fff 245 #define D64_RS0_RS_MASK 0xf0000000 246 #define D64_RS0_RS_SHIFT 28 247 #define D64_RS0_RS_DISABLED 0x00000000 248 #define D64_RS0_RS_ACTIVE 0x10000000 249 #define D64_RS0_RS_IDLE 0x20000000 250 #define D64_RS0_RS_STOPPED 0x30000000 251 #define D64_RS0_RS_SUSP 0x40000000 252 253 #define D64_RS1_AD_MASK 0x0001ffff 254 #define D64_RS1_RE_MASK 0xf0000000 255 #define D64_RS1_RE_SHIFT 28 256 #define D64_RS1_RE_NOERR 0x00000000 257 #define D64_RS1_RE_DPO 0x10000000 258 #define D64_RS1_RE_DFU 0x20000000 259 #define D64_RS1_RE_DTE 0x30000000 260 #define D64_RS1_RE_DESRE 0x40000000 261 #define D64_RS1_RE_COREE 0x50000000 262 263 264 #define D64_FA_OFF_MASK 0xffff 265 #define D64_FA_SEL_MASK 0xf0000 266 #define D64_FA_SEL_SHIFT 16 267 #define D64_FA_SEL_XDD 0x00000 268 #define D64_FA_SEL_XDP 0x10000 269 #define D64_FA_SEL_RDD 0x40000 270 #define D64_FA_SEL_RDP 0x50000 271 #define D64_FA_SEL_XFD 0x80000 272 #define D64_FA_SEL_XFP 0x90000 273 #define D64_FA_SEL_RFD 0xc0000 274 #define D64_FA_SEL_RFP 0xd0000 275 #define D64_FA_SEL_RSD 0xe0000 276 #define D64_FA_SEL_RSP 0xf0000 277 278 279 #define D64_CTRL1_EOT ((uint32)1 << 28) 280 #define D64_CTRL1_IOC ((uint32)1 << 29) 281 #define D64_CTRL1_EOF ((uint32)1 << 30) 282 #define D64_CTRL1_SOF ((uint32)1 << 31) 283 284 285 #define D64_CTRL2_BC_MASK 0x00007fff 286 #define D64_CTRL2_AE 0x00030000 287 #define D64_CTRL2_AE_SHIFT 16 288 #define D64_CTRL2_PARITY 0x00040000 289 290 291 #define D64_CTRL_CORE_MASK 0x0ff00000 292 293 294 #endif 295
