1 /* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in 12 * the documentation and/or other materials provided with the 13 * distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __ASM_ARCH_MSM7200_GPIO_H 30 #define __ASM_ARCH_MSM7200_GPIO_H 31 32 #define MSM_GPIO1_BASE 0xA9200000 33 #define MSM_GPIO2_BASE 0xA9300000 34 35 /* see 80-VA736-2 Rev C pp 695-751 36 ** 37 ** These are actually the *shadow* gpio registers, since the 38 ** real ones (which allow full access) are only available to the 39 ** ARM9 side of the world. 40 ** 41 ** Since the _BASE need to be page-aligned when we're mapping them 42 ** to virtual addresses, adjust for the additional offset in these 43 ** macros. 44 */ 45 46 #define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) 47 #define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) 48 49 /* output value */ 50 #define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */ 51 #define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */ 52 #define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */ 53 #define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */ 54 #define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */ 55 56 /* same pin map as above, output enable */ 57 #define GPIO_OE_0 GPIO1_REG(0x10) 58 #define GPIO_OE_1 GPIO2_REG(0x08) 59 #define GPIO_OE_2 GPIO1_REG(0x14) 60 #define GPIO_OE_3 GPIO1_REG(0x18) 61 #define GPIO_OE_4 GPIO1_REG(0x1C) 62 63 /* same pin map as above, input read */ 64 #define GPIO_IN_0 GPIO1_REG(0x34) 65 #define GPIO_IN_1 GPIO2_REG(0x20) 66 #define GPIO_IN_2 GPIO1_REG(0x38) 67 #define GPIO_IN_3 GPIO1_REG(0x3C) 68 #define GPIO_IN_4 GPIO1_REG(0x40) 69 70 /* same pin map as above, 1=edge 0=level interrup */ 71 #define GPIO_INT_EDGE_0 GPIO1_REG(0x60) 72 #define GPIO_INT_EDGE_1 GPIO2_REG(0x50) 73 #define GPIO_INT_EDGE_2 GPIO1_REG(0x64) 74 #define GPIO_INT_EDGE_3 GPIO1_REG(0x68) 75 #define GPIO_INT_EDGE_4 GPIO1_REG(0x6C) 76 77 /* same pin map as above, 1=positive 0=negative */ 78 #define GPIO_INT_POS_0 GPIO1_REG(0x70) 79 #define GPIO_INT_POS_1 GPIO2_REG(0x58) 80 #define GPIO_INT_POS_2 GPIO1_REG(0x74) 81 #define GPIO_INT_POS_3 GPIO1_REG(0x78) 82 #define GPIO_INT_POS_4 GPIO1_REG(0x7C) 83 84 /* same pin map as above, interrupt enable */ 85 #define GPIO_INT_EN_0 GPIO1_REG(0x80) 86 #define GPIO_INT_EN_1 GPIO2_REG(0x60) 87 #define GPIO_INT_EN_2 GPIO1_REG(0x84) 88 #define GPIO_INT_EN_3 GPIO1_REG(0x88) 89 #define GPIO_INT_EN_4 GPIO1_REG(0x8C) 90 91 /* same pin map as above, write 1 to clear interrupt */ 92 #define GPIO_INT_CLEAR_0 GPIO1_REG(0x90) 93 #define GPIO_INT_CLEAR_1 GPIO2_REG(0x68) 94 #define GPIO_INT_CLEAR_2 GPIO1_REG(0x94) 95 #define GPIO_INT_CLEAR_3 GPIO1_REG(0x98) 96 #define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C) 97 98 /* same pin map as above, 1=interrupt pending */ 99 #define GPIO_INT_STATUS_0 GPIO1_REG(0xA0) 100 #define GPIO_INT_STATUS_1 GPIO2_REG(0x70) 101 #define GPIO_INT_STATUS_2 GPIO1_REG(0xA4) 102 #define GPIO_INT_STATUS_3 GPIO1_REG(0xA8) 103 #define GPIO_INT_STATUS_4 GPIO1_REG(0xAC) 104 105 #endif 106
