1 %verify "executed" 2 /* 3 * Signed 64-bit integer multiply. 4 * 5 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 6 * WX 7 * x YZ 8 * -------- 9 * ZW ZX 10 * YW YX 11 * 12 * The low word of the result holds ZX, the high word holds 13 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 14 * it doesn't fit in the low 64 bits. 15 * 16 * Unlike most ARM math operations, multiply instructions have 17 * restrictions on using the same register more than once (Rd and Rm 18 * cannot be the same). 19 */ 20 /* mul-long vAA, vBB, vCC */ 21 FETCH(r0, 1) @ r0<- CCBB 22 and r2, r0, #255 @ r2<- BB 23 mov r3, r0, lsr #8 @ r3<- CC 24 add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 25 add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 26 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 27 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 28 mul ip, r2, r1 @ ip<- ZxW 29 umull r9, r10, r2, r0 @ r9/r10 <- ZxX 30 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 31 mov r0, rINST, lsr #8 @ r0<- AA 32 add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 33 add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 34 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 35 b .L${opcode}_finish 36 %break 37 38 .L${opcode}_finish: 39 GET_INST_OPCODE(ip) @ extract opcode from rINST 40 stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 41 GOTO_OPCODE(ip) @ jump to next instruction 42
