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      1 %verify "executed"
      2     /*
      3      * Long integer shift.  This is different from the generic 32/64-bit
      4      * binary operations because vAA/vBB are 64-bit but vCC (the shift
      5      * distance) is 32-bit.  Also, Dalvik requires us to mask off the low
      6      * 6 bits of the shift distance.
      7      */
      8     /* shl-long vAA, vBB, vCC */
      9     FETCH(r0, 1)                        @ r0<- CCBB
     10     mov     r9, rINST, lsr #8           @ r9<- AA
     11     and     r3, r0, #255                @ r3<- BB
     12     mov     r0, r0, lsr #8              @ r0<- CC
     13     add     r3, rFP, r3, lsl #2         @ r3<- &fp[BB]
     14     GET_VREG(r2, r0)                    @ r2<- vCC
     15     ldmia   r3, {r0-r1}                 @ r0/r1<- vBB/vBB+1
     16     and     r2, r2, #63                 @ r2<- r2 & 0x3f
     17     add     r9, rFP, r9, lsl #2         @ r9<- &fp[AA]
     18 
     19     mov     r1, r1, asl r2              @  r1<- r1 << r2
     20     rsb     r3, r2, #32                 @  r3<- 32 - r2
     21     orr     r1, r1, r0, lsr r3          @  r1<- r1 | (r0 << (32-r2))
     22     subs    ip, r2, #32                 @  ip<- r2 - 32
     23     movpl   r1, r0, asl ip              @  if r2 >= 32, r1<- r0 << (r2-32)
     24     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
     25     b       .L${opcode}_finish
     26 %break
     27 
     28 .L${opcode}_finish:
     29     mov     r0, r0, asl r2              @  r0<- r0 << r2
     30     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     31     stmia   r9, {r0-r1}                 @ vAA/vAA+1<- r0/r1
     32     GOTO_OPCODE(ip)                     @ jump to next instruction
     33