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      1 %default {"preinstr":"", "result":"r0", "chkzero":"0"}
      2     /*
      3      * Generic 32-bit "/2addr" binary operation.  Provide an "instr" line
      4      * that specifies an instruction that performs "result = r0 op r1".
      5      * This could be an ARM instruction or a function call.  (If the result
      6      * comes back in a register other than r0, you can override "result".)
      7      *
      8      * If "chkzero" is set to 1, we perform a divide-by-zero check on
      9      * vCC (r1).  Useful for integer division and modulus.
     10      *
     11      * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr,
     12      *      rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr,
     13      *      shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr,
     14      *      sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr
     15      */
     16     /* binop/2addr vA, vB */
     17     mov     r9, rINST, lsr #8           @ r9<- A+
     18     mov     r3, rINST, lsr #12          @ r3<- B
     19     and     r9, r9, #15
     20     GET_VREG(r1, r3)                    @ r1<- vB
     21     GET_VREG(r0, r9)                    @ r0<- vA
     22     .if $chkzero
     23     cmp     r1, #0                      @ is second operand zero?
     24     beq     common_errDivideByZero
     25     .endif
     26     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
     27 
     28     $preinstr                           @ optional op; may set condition codes
     29     $instr                              @ $result<- op, r0-r3 changed
     30     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     31     SET_VREG($result, r9)               @ vAA<- $result
     32     GOTO_OPCODE(ip)                     @ jump to next instruction
     33     /* 10-13 instructions */
     34