1 %default {"preinstr":"", "result":"r0", "chkzero":"0"} 2 /* 3 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 4 * that specifies an instruction that performs "result = r0 op r1". 5 * This could be an ARM instruction or a function call. (If the result 6 * comes back in a register other than r0, you can override "result".) 7 * 8 * If "chkzero" is set to 1, we perform a divide-by-zero check on 9 * vCC (r1). Useful for integer division and modulus. 10 * 11 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 12 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 13 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 14 */ 15 /* binop/lit8 vAA, vBB, #+CC */ 16 FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 17 mov r9, rINST, lsr #8 @ r9<- AA 18 and r2, r3, #255 @ r2<- BB 19 GET_VREG(r0, r2) @ r0<- vBB 20 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 21 .if $chkzero 22 @cmp r1, #0 @ is second operand zero? 23 beq common_errDivideByZero 24 .endif 25 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 26 27 $preinstr @ optional op; may set condition codes 28 $instr @ $result<- op, r0-r3 changed 29 GET_INST_OPCODE(ip) @ extract opcode from rINST 30 SET_VREG($result, r9) @ vAA<- $result 31 GOTO_OPCODE(ip) @ jump to next instruction 32 /* 10-12 instructions */ 33
