1 /* Copyright (C) 2007-2008 The Android Open Source Project 2 ** 3 ** This software is licensed under the terms of the GNU General Public 4 ** License version 2, as published by the Free Software Foundation, and 5 ** may be copied, distributed, and modified under those terms. 6 ** 7 ** This program is distributed in the hope that it will be useful, 8 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 9 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 ** GNU General Public License for more details. 11 */ 12 #include "hw.h" 13 #include "boards.h" 14 #include "devices.h" 15 #include "net.h" 16 #include "arm_pic.h" 17 #include "sysemu.h" 18 #include "goldfish_device.h" 19 #include "android/globals.h" 20 #include "audio/audio.h" 21 #include "arm-misc.h" 22 #include "console.h" 23 #ifdef CONFIG_MEMCHECK 24 #include "memcheck/memcheck_api.h" 25 #endif // CONFIG_MEMCHECK 26 27 #include "android/utils/debug.h" 28 29 #define D(...) VERBOSE_PRINT(init,__VA_ARGS__) 30 31 #define ARM_CPU_SAVE_VERSION 1 32 33 char* audio_input_source = NULL; 34 35 void goldfish_memlog_init(uint32_t base); 36 37 static struct goldfish_device event0_device = { 38 .name = "goldfish_events", 39 .id = 0, 40 .size = 0x1000, 41 .irq_count = 1 42 }; 43 44 static struct goldfish_device nand_device = { 45 .name = "goldfish_nand", 46 .id = 0, 47 .size = 0x1000 48 }; 49 50 /* Board init. */ 51 52 #define TEST_SWITCH 1 53 #if TEST_SWITCH 54 uint32_t switch_test_write(void *opaque, uint32_t state) 55 { 56 goldfish_switch_set_state(opaque, state); 57 return state; 58 } 59 #endif 60 static void android_arm_init_(ram_addr_t ram_size, 61 const char *boot_device, 62 const char *kernel_filename, 63 const char *kernel_cmdline, 64 const char *initrd_filename, 65 const char *cpu_model) 66 { 67 CPUState *env; 68 qemu_irq *cpu_pic; 69 qemu_irq *goldfish_pic; 70 int i; 71 struct arm_boot_info info; 72 ram_addr_t ram_offset; 73 DisplayState* ds = get_displaystate(); 74 75 if (!cpu_model) 76 cpu_model = "arm926"; 77 78 env = cpu_init(cpu_model); 79 register_savevm( "cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load, env ); 80 81 ram_offset = qemu_ram_alloc(ram_size); 82 cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); 83 84 cpu_pic = arm_pic_init_cpu(env); 85 goldfish_pic = goldfish_interrupt_init(0xff000000, cpu_pic[ARM_PIC_CPU_IRQ], cpu_pic[ARM_PIC_CPU_FIQ]); 86 goldfish_device_init(goldfish_pic, 0xff010000, 0x7f0000, 10, 22); 87 88 goldfish_device_bus_init(0xff001000, 1); 89 90 goldfish_timer_and_rtc_init(0xff003000, 3); 91 92 goldfish_tty_add(serial_hds[0], 0, 0xff002000, 4); 93 for(i = 1; i < MAX_SERIAL_PORTS; i++) { 94 //printf("android_arm_init serial %d %x\n", i, serial_hds[i]); 95 if(serial_hds[i]) { 96 goldfish_tty_add(serial_hds[i], i, 0, 0); 97 } 98 } 99 100 for(i = 0; i < MAX_NICS; i++) { 101 if (nd_table[i].vlan) { 102 if (nd_table[i].model == NULL 103 || strcmp(nd_table[i].model, "smc91c111") == 0) { 104 struct goldfish_device *smc_device; 105 smc_device = qemu_mallocz(sizeof(*smc_device)); 106 smc_device->name = "smc91x"; 107 smc_device->id = i; 108 smc_device->size = 0x1000; 109 smc_device->irq_count = 1; 110 goldfish_add_device_no_io(smc_device); 111 smc91c111_init(&nd_table[i], smc_device->base, goldfish_pic[smc_device->irq]); 112 } else { 113 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); 114 exit (1); 115 } 116 } 117 } 118 119 goldfish_fb_init(ds, 0); 120 #ifdef HAS_AUDIO 121 goldfish_audio_init(0xff004000, 0, audio_input_source); 122 #endif 123 { 124 int idx = drive_get_index( IF_IDE, 0, 0 ); 125 if (idx >= 0) 126 goldfish_mmc_init(0xff005000, 0, drives_table[idx].bdrv); 127 } 128 129 goldfish_memlog_init(0xff006000); 130 131 if (android_hw->hw_battery) 132 goldfish_battery_init(); 133 134 goldfish_add_device_no_io(&event0_device); 135 events_dev_init(event0_device.base, goldfish_pic[event0_device.irq]); 136 137 #ifdef CONFIG_NAND 138 goldfish_add_device_no_io(&nand_device); 139 nand_dev_init(nand_device.base); 140 #endif 141 #ifdef CONFIG_TRACE 142 extern const char *trace_filename; 143 /* Init trace device if either tracing, or memory checking is enabled. */ 144 if (trace_filename != NULL 145 #ifdef CONFIG_MEMCHECK 146 || memcheck_enabled 147 #endif // CONFIG_MEMCHECK 148 ) { 149 trace_dev_init(); 150 } 151 if (trace_filename != NULL) { 152 D( "Trace file name is set to %s\n", trace_filename ); 153 } else { 154 D("Trace file name is not set\n"); 155 } 156 #endif 157 158 #if TEST_SWITCH 159 { 160 void *sw; 161 sw = goldfish_switch_add("test", NULL, NULL, 0); 162 goldfish_switch_set_state(sw, 1); 163 goldfish_switch_add("test2", switch_test_write, sw, 1); 164 } 165 #endif 166 167 memset(&info, 0, sizeof info); 168 info.ram_size = ram_size; 169 info.kernel_filename = kernel_filename; 170 info.kernel_cmdline = kernel_cmdline; 171 info.initrd_filename = initrd_filename; 172 info.nb_cpus = 1; 173 info.board_id = 1441; 174 175 arm_load_kernel(env, &info); 176 } 177 178 QEMUMachine android_arm_machine = { 179 "android_arm", 180 "ARM Android Emulator", 181 android_arm_init_, 182 0, 183 0, 184 1, 185 NULL 186 }; 187 188 static void android_arm_init(void) 189 { 190 qemu_register_machine(&android_arm_machine); 191 } 192 193 machine_init(android_arm_init); 194
