1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 6 and Martin Simmons (@harleqn.co.uk). 7 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 8 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 9 10 This file is part of GCC. 11 12 GCC is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published 14 by the Free Software Foundation; either version 3, or (at your 15 option) any later version. 16 17 GCC is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with GCC; see the file COPYING3. If not see 24 <http://www.gnu.org/licenses/>. */ 25 26 #ifndef GCC_ARM_H 27 #define GCC_ARM_H 28 29 #include "config/vxworks-dummy.h" 30 31 /* The architecture define. */ 32 extern char arm_arch_name[]; 33 34 /* Target CPU builtins. */ 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do \ 37 { \ 38 /* Define __arm__ even when in thumb mode, for \ 39 consistency with armcc. */ \ 40 builtin_define ("__arm__"); \ 41 builtin_define ("__APCS_32__"); \ 42 if (TARGET_THUMB) \ 43 builtin_define ("__thumb__"); \ 44 if (TARGET_THUMB2) \ 45 builtin_define ("__thumb2__"); \ 46 \ 47 if (TARGET_BIG_END) \ 48 { \ 49 builtin_define ("__ARMEB__"); \ 50 if (TARGET_THUMB) \ 51 builtin_define ("__THUMBEB__"); \ 52 if (TARGET_LITTLE_WORDS) \ 53 builtin_define ("__ARMWEL__"); \ 54 } \ 55 else \ 56 { \ 57 builtin_define ("__ARMEL__"); \ 58 if (TARGET_THUMB) \ 59 builtin_define ("__THUMBEL__"); \ 60 } \ 61 \ 62 if (TARGET_SOFT_FLOAT) \ 63 builtin_define ("__SOFTFP__"); \ 64 \ 65 if (TARGET_VFP) \ 66 builtin_define ("__VFP_FP__"); \ 67 \ 68 if (TARGET_NEON) \ 69 builtin_define ("__ARM_NEON__"); \ 70 \ 71 /* Add a define for interworking. \ 72 Needed when building libgcc.a. */ \ 73 if (arm_cpp_interwork) \ 74 builtin_define ("__THUMB_INTERWORK__"); \ 75 \ 76 builtin_assert ("cpu=arm"); \ 77 builtin_assert ("machine=arm"); \ 78 \ 79 builtin_define (arm_arch_name); \ 80 if (arm_arch_cirrus) \ 81 builtin_define ("__MAVERICK__"); \ 82 if (arm_arch_xscale) \ 83 builtin_define ("__XSCALE__"); \ 84 if (arm_arch_iwmmxt) \ 85 builtin_define ("__IWMMXT__"); \ 86 if (TARGET_AAPCS_BASED) \ 87 builtin_define ("__ARM_EABI__"); \ 88 } while (0) 89 90 /* The various ARM cores. */ 91 enum processor_type 92 { 93 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 94 IDENT, 95 #include "arm-cores.def" 96 #undef ARM_CORE 97 /* Used to indicate that no processor has been specified. */ 98 arm_none 99 }; 100 101 enum target_cpus 102 { 103 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 104 TARGET_CPU_##IDENT, 105 #include "arm-cores.def" 106 #undef ARM_CORE 107 TARGET_CPU_generic 108 }; 109 110 /* The processor for which instructions should be scheduled. */ 111 extern enum processor_type arm_tune; 112 113 typedef enum arm_cond_code 114 { 115 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 116 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 117 } 118 arm_cc; 119 120 extern arm_cc arm_current_cc; 121 122 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 123 124 extern int arm_target_label; 125 extern int arm_ccfsm_state; 126 extern GTY(()) rtx arm_target_insn; 127 /* Define the information needed to generate branch insns. This is 128 stored from the compare operation. */ 129 extern GTY(()) rtx arm_compare_op0; 130 extern GTY(()) rtx arm_compare_op1; 131 /* The label of the current constant pool. */ 132 extern rtx pool_vector_label; 133 /* Set to 1 when a return insn is output, this means that the epilogue 134 is not needed. */ 135 extern int return_used_this_function; 136 /* Callback to output language specific object attributes. */ 137 extern void (*arm_lang_output_object_attributes_hook)(void); 138 139 /* Just in case configure has failed to define anything. */ 141 #ifndef TARGET_CPU_DEFAULT 142 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 143 #endif 144 145 146 #undef CPP_SPEC 147 #define CPP_SPEC "%(subtarget_cpp_spec) \ 148 %{msoft-float:%{mhard-float: \ 149 %e-msoft-float and -mhard_float may not be used together}} \ 150 %{mbig-endian:%{mlittle-endian: \ 151 %e-mbig-endian and -mlittle-endian may not be used together}}" 152 153 #ifndef CC1_SPEC 154 #define CC1_SPEC "" 155 #endif 156 157 /* This macro defines names of additional specifications to put in the specs 158 that can be used in various specifications like CC1_SPEC. Its definition 159 is an initializer with a subgrouping for each command option. 160 161 Each subgrouping contains a string constant, that defines the 162 specification name, and a string constant that used by the GCC driver 163 program. 164 165 Do not define this macro if it does not need to do anything. */ 166 #define EXTRA_SPECS \ 167 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 168 SUBTARGET_EXTRA_SPECS 169 170 #ifndef SUBTARGET_EXTRA_SPECS 171 #define SUBTARGET_EXTRA_SPECS 172 #endif 173 174 #ifndef SUBTARGET_CPP_SPEC 175 #define SUBTARGET_CPP_SPEC "" 176 #endif 177 178 /* Run-time Target Specification. */ 180 #ifndef TARGET_VERSION 181 #define TARGET_VERSION fputs (" (ARM/generic)", stderr); 182 #endif 183 184 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 185 /* Use hardware floating point instructions. */ 186 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 187 /* Use hardware floating point calling convention. */ 188 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 189 #define TARGET_FPA (arm_fp_model == ARM_FP_MODEL_FPA) 190 #define TARGET_MAVERICK (arm_fp_model == ARM_FP_MODEL_MAVERICK) 191 #define TARGET_VFP (arm_fp_model == ARM_FP_MODEL_VFP) 192 #define TARGET_IWMMXT (arm_arch_iwmmxt) 193 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 194 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 195 #define TARGET_ARM (! TARGET_THUMB) 196 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 197 #define TARGET_BACKTRACE (leaf_function_p () \ 198 ? TARGET_TPCS_LEAF_FRAME \ 199 : TARGET_TPCS_FRAME) 200 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) 201 #define TARGET_AAPCS_BASED \ 202 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 203 204 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 205 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 206 207 /* Only 16-bit thumb code. */ 208 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 209 /* Arm or Thumb-2 32-bit code. */ 210 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 211 /* 32-bit Thumb-2 code. */ 212 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 213 /* Thumb-1 only. */ 214 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 215 216 /* The following two macros concern the ability to execute coprocessor 217 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 218 only ever tested when we know we are generating for VFP hardware; we need 219 to be more careful with TARGET_NEON as noted below. */ 220 221 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 222 #define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \ 223 && (arm_fpu_arch == FPUTYPE_VFP3 \ 224 || arm_fpu_arch == FPUTYPE_NEON)) 225 226 /* FPU supports VFPv3 instructions. */ 227 #define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \ 228 && (arm_fpu_arch == FPUTYPE_VFP3D16 \ 229 || TARGET_VFPD32)) 230 231 /* FPU supports Neon instructions. The setting of this macro gets 232 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 233 and TARGET_HARD_FLOAT to ensure that NEON instructions are 234 available. */ 235 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 236 && arm_fp_model == ARM_FP_MODEL_VFP \ 237 && arm_fpu_arch == FPUTYPE_NEON) 238 239 /* "DSP" multiply instructions, eg. SMULxy. */ 240 #define TARGET_DSP_MULTIPLY \ 241 (TARGET_32BIT && arm_arch5e && arm_arch_notm) 242 /* Integer SIMD instructions, and extend-accumulate instructions. */ 243 #define TARGET_INT_SIMD \ 244 (TARGET_32BIT && arm_arch6 && arm_arch_notm) 245 246 /* Should MOVW/MOVT be used in preference to a constant pool. */ 247 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) 248 249 /* We could use unified syntax for arm mode, but for now we just use it 250 for Thumb-2. */ 251 #define TARGET_UNIFIED_ASM TARGET_THUMB2 252 253 254 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 255 then TARGET_AAPCS_BASED must be true -- but the converse does not 256 hold. TARGET_BPABI implies the use of the BPABI runtime library, 257 etc., in addition to just the AAPCS calling conventions. */ 258 #ifndef TARGET_BPABI 259 #define TARGET_BPABI false 260 #endif 261 262 /* Support for a compile-time default CPU, et cetera. The rules are: 263 --with-arch is ignored if -march or -mcpu are specified. 264 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 265 by --with-arch. 266 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 267 by -march). 268 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are 269 specified. 270 --with-fpu is ignored if -mfpu is specified. 271 --with-abi is ignored is -mabi is specified. */ 272 #define OPTION_DEFAULT_SPECS \ 273 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 274 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 275 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 276 {"float", \ 277 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ 278 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 279 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 280 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, 281 282 /* Which floating point model to use. */ 283 enum arm_fp_model 284 { 285 ARM_FP_MODEL_UNKNOWN, 286 /* FPA model (Hardware or software). */ 287 ARM_FP_MODEL_FPA, 288 /* Cirrus Maverick floating point model. */ 289 ARM_FP_MODEL_MAVERICK, 290 /* VFP floating point model. */ 291 ARM_FP_MODEL_VFP 292 }; 293 294 extern enum arm_fp_model arm_fp_model; 295 296 /* Which floating point hardware is available. Also update 297 fp_model_for_fpu in arm.c when adding entries to this list. */ 298 enum fputype 299 { 300 /* No FP hardware. */ 301 FPUTYPE_NONE, 302 /* Full FPA support. */ 303 FPUTYPE_FPA, 304 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ 305 FPUTYPE_FPA_EMU2, 306 /* Emulated FPA hardware, Issue 3 emulator. */ 307 FPUTYPE_FPA_EMU3, 308 /* Cirrus Maverick floating point co-processor. */ 309 FPUTYPE_MAVERICK, 310 /* VFP. */ 311 FPUTYPE_VFP, 312 /* VFPv3-D16. */ 313 FPUTYPE_VFP3D16, 314 /* VFPv3. */ 315 FPUTYPE_VFP3, 316 /* Neon. */ 317 FPUTYPE_NEON 318 }; 319 320 /* Recast the floating point class to be the floating point attribute. */ 321 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) 322 323 /* What type of floating point to tune for */ 324 extern enum fputype arm_fpu_tune; 325 326 /* What type of floating point instructions are available */ 327 extern enum fputype arm_fpu_arch; 328 329 enum float_abi_type 330 { 331 ARM_FLOAT_ABI_SOFT, 332 ARM_FLOAT_ABI_SOFTFP, 333 ARM_FLOAT_ABI_HARD 334 }; 335 336 extern enum float_abi_type arm_float_abi; 337 338 #ifndef TARGET_DEFAULT_FLOAT_ABI 339 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 340 #endif 341 342 /* Which ABI to use. */ 343 enum arm_abi_type 344 { 345 ARM_ABI_APCS, 346 ARM_ABI_ATPCS, 347 ARM_ABI_AAPCS, 348 ARM_ABI_IWMMXT, 349 ARM_ABI_AAPCS_LINUX 350 }; 351 352 extern enum arm_abi_type arm_abi; 353 354 #ifndef ARM_DEFAULT_ABI 355 #define ARM_DEFAULT_ABI ARM_ABI_APCS 356 #endif 357 358 /* Which thread pointer access sequence to use. */ 359 enum arm_tp_type { 360 TP_AUTO, 361 TP_SOFT, 362 TP_CP15 363 }; 364 365 extern enum arm_tp_type target_thread_pointer; 366 367 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 368 extern int arm_arch3m; 369 370 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 371 extern int arm_arch4; 372 373 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 374 extern int arm_arch4t; 375 376 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 377 extern int arm_arch5; 378 379 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 380 extern int arm_arch5e; 381 382 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 383 extern int arm_arch6; 384 385 /* Nonzero if instructions not present in the 'M' profile can be used. */ 386 extern int arm_arch_notm; 387 388 /* Nonzero if this chip can benefit from load scheduling. */ 389 extern int arm_ld_sched; 390 391 /* Nonzero if generating thumb code. */ 392 extern int thumb_code; 393 394 /* Nonzero if this chip is a StrongARM. */ 395 extern int arm_tune_strongarm; 396 397 /* Nonzero if this chip is a Cirrus variant. */ 398 extern int arm_arch_cirrus; 399 400 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 401 extern int arm_arch_iwmmxt; 402 403 /* Nonzero if this chip is an XScale. */ 404 extern int arm_arch_xscale; 405 406 /* Nonzero if tuning for XScale. */ 407 extern int arm_tune_xscale; 408 409 /* Nonzero if tuning for stores via the write buffer. */ 410 extern int arm_tune_wbuf; 411 412 /* Nonzero if tuning for Cortex-A9. */ 413 extern int arm_tune_cortex_a9; 414 415 /* Nonzero if we should define __THUMB_INTERWORK__ in the 416 preprocessor. 417 XXX This is a bit of a hack, it's intended to help work around 418 problems in GLD which doesn't understand that armv5t code is 419 interworking clean. */ 420 extern int arm_cpp_interwork; 421 422 /* Nonzero if chip supports Thumb 2. */ 423 extern int arm_arch_thumb2; 424 425 /* Nonzero if chip supports integer division instruction. */ 426 extern int arm_arch_hwdiv; 427 428 #ifndef TARGET_DEFAULT 429 #define TARGET_DEFAULT (MASK_APCS_FRAME) 430 #endif 431 432 /* The frame pointer register used in gcc has nothing to do with debugging; 433 that is controlled by the APCS-FRAME option. */ 434 #define CAN_DEBUG_WITHOUT_FP 435 436 #define OVERRIDE_OPTIONS arm_override_options () 437 438 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 439 arm_optimization_options ((LEVEL), (SIZE)) 440 441 /* Nonzero if PIC code requires explicit qualifiers to generate 442 PLT and GOT relocs rather than the assembler doing so implicitly. 443 Subtargets can override these if required. */ 444 #ifndef NEED_GOT_RELOC 445 #define NEED_GOT_RELOC 0 446 #endif 447 #ifndef NEED_PLT_RELOC 448 #define NEED_PLT_RELOC 0 449 #endif 450 451 /* Nonzero if we need to refer to the GOT with a PC-relative 452 offset. In other words, generate 453 454 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 455 456 rather than 457 458 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 459 460 The default is true, which matches NetBSD. Subtargets can 461 override this if required. */ 462 #ifndef GOT_PCREL 463 #define GOT_PCREL 1 464 #endif 465 466 /* Target machine storage Layout. */ 468 469 470 /* Define this macro if it is advisable to hold scalars in registers 471 in a wider mode than that declared by the program. In such cases, 472 the value is constrained to be within the bounds of the declared 473 type, but kept valid in the wider mode. The signedness of the 474 extension may differ from that of the type. */ 475 476 /* It is far faster to zero extend chars than to sign extend them */ 477 478 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 479 if (GET_MODE_CLASS (MODE) == MODE_INT \ 480 && GET_MODE_SIZE (MODE) < 4) \ 481 { \ 482 if (MODE == QImode) \ 483 UNSIGNEDP = 1; \ 484 else if (MODE == HImode) \ 485 UNSIGNEDP = 1; \ 486 (MODE) = SImode; \ 487 } 488 489 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ 490 if ((GET_MODE_CLASS (MODE) == MODE_INT \ 491 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT) \ 492 && GET_MODE_SIZE (MODE) < 4) \ 493 (MODE) = SImode; \ 494 495 /* Define this if most significant bit is lowest numbered 496 in instructions that operate on numbered bit-fields. */ 497 #define BITS_BIG_ENDIAN 0 498 499 /* Define this if most significant byte of a word is the lowest numbered. 500 Most ARM processors are run in little endian mode, so that is the default. 501 If you want to have it run-time selectable, change the definition in a 502 cover file to be TARGET_BIG_ENDIAN. */ 503 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 504 505 /* Define this if most significant word of a multiword number is the lowest 506 numbered. 507 This is always false, even when in big-endian mode. */ 508 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 509 510 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 511 on processor pre-defineds when compiling libgcc2.c. */ 512 #if defined(__ARMEB__) && !defined(__ARMWEL__) 513 #define LIBGCC2_WORDS_BIG_ENDIAN 1 514 #else 515 #define LIBGCC2_WORDS_BIG_ENDIAN 0 516 #endif 517 518 /* Define this if most significant word of doubles is the lowest numbered. 519 The rules are different based on whether or not we use FPA-format, 520 VFP-format or some other floating point co-processor's format doubles. */ 521 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 522 523 #define UNITS_PER_WORD 4 524 525 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword 526 registers when autovectorizing for Neon, at least until multiple vector 527 widths are supported properly by the middle-end. */ 528 #define UNITS_PER_SIMD_WORD(MODE) \ 529 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) 530 531 /* True if natural alignment is used for doubleword types. */ 532 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 533 534 #define DOUBLEWORD_ALIGNMENT 64 535 536 #define PARM_BOUNDARY 32 537 538 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 539 540 #define PREFERRED_STACK_BOUNDARY \ 541 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 542 543 #define FUNCTION_BOUNDARY 32 544 545 /* The lowest bit is used to indicate Thumb-mode functions, so the 546 vbit must go into the delta field of pointers to member 547 functions. */ 548 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 549 550 #define EMPTY_FIELD_BOUNDARY 32 551 552 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 553 554 /* XXX Blah -- this macro is used directly by libobjc. Since it 555 supports no vector modes, cut out the complexity and fall back 556 on BIGGEST_FIELD_ALIGNMENT. */ 557 #ifdef IN_TARGET_LIBS 558 #define BIGGEST_FIELD_ALIGNMENT 64 559 #endif 560 561 /* Make strings word-aligned so strcpy from constants will be faster. */ 562 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 563 564 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 565 ((TREE_CODE (EXP) == STRING_CST \ 566 && !optimize_size \ 567 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 568 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 569 570 /* Align definitions of arrays, unions and structures so that 571 initializations and copies can be made more efficient. This is not 572 ABI-changing, so it only affects places where we can see the 573 definition. */ 574 #define DATA_ALIGNMENT(EXP, ALIGN) \ 575 ((((ALIGN) < BITS_PER_WORD) \ 576 && (TREE_CODE (EXP) == ARRAY_TYPE \ 577 || TREE_CODE (EXP) == UNION_TYPE \ 578 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 579 580 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 581 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 582 583 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 584 value set in previous versions of this toolchain was 8, which produces more 585 compact structures. The command line option -mstructure_size_boundary=<n> 586 can be used to change this value. For compatibility with the ARM SDK 587 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 588 0020D) page 2-20 says "Structures are aligned on word boundaries". 589 The AAPCS specifies a value of 8. */ 590 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 591 extern int arm_structure_size_boundary; 592 593 /* This is the value used to initialize arm_structure_size_boundary. If a 594 particular arm target wants to change the default value it should change 595 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 596 for an example of this. */ 597 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 598 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 599 #endif 600 601 /* Nonzero if move instructions will actually fail to work 602 when given unaligned data. */ 603 #define STRICT_ALIGNMENT 1 604 605 /* wchar_t is unsigned under the AAPCS. */ 606 #ifndef WCHAR_TYPE 607 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 608 609 #define WCHAR_TYPE_SIZE BITS_PER_WORD 610 #endif 611 612 #ifndef SIZE_TYPE 613 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 614 #endif 615 616 #ifndef PTRDIFF_TYPE 617 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 618 #endif 619 620 /* AAPCS requires that structure alignment is affected by bitfields. */ 621 #ifndef PCC_BITFIELD_TYPE_MATTERS 622 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 623 #endif 624 625 626 /* Standard register usage. */ 628 629 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 630 (S - saved over call). 631 632 r0 * argument word/integer result 633 r1-r3 argument word 634 635 r4-r8 S register variable 636 r9 S (rfp) register variable (real frame pointer) 637 638 r10 F S (sl) stack limit (used by -mapcs-stack-check) 639 r11 F S (fp) argument pointer 640 r12 (ip) temp workspace 641 r13 F S (sp) lower end of current stack frame 642 r14 (lr) link address/workspace 643 r15 F (pc) program counter 644 645 f0 floating point result 646 f1-f3 floating point scratch 647 648 f4-f7 S floating point variable 649 650 cc This is NOT a real register, but is used internally 651 to represent things that use or set the condition 652 codes. 653 sfp This isn't either. It is used during rtl generation 654 since the offset between the frame pointer and the 655 auto's isn't known until after register allocation. 656 afp Nor this, we only need this because of non-local 657 goto. Without it fp appears to be used and the 658 elimination code won't get rid of sfp. It tracks 659 fp exactly at all times. 660 661 *: See CONDITIONAL_REGISTER_USAGE */ 662 663 /* 664 mvf0 Cirrus floating point result 665 mvf1-mvf3 Cirrus floating point scratch 666 mvf4-mvf15 S Cirrus floating point variable. */ 667 668 /* s0-s15 VFP scratch (aka d0-d7). 669 s16-s31 S VFP variable (aka d8-d15). 670 vfpcc Not a real register. Represents the VFP condition 671 code flags. */ 672 673 /* The stack backtrace structure is as follows: 674 fp points to here: | save code pointer | [fp] 675 | return link value | [fp, #-4] 676 | return sp value | [fp, #-8] 677 | return fp value | [fp, #-12] 678 [| saved r10 value |] 679 [| saved r9 value |] 680 [| saved r8 value |] 681 [| saved r7 value |] 682 [| saved r6 value |] 683 [| saved r5 value |] 684 [| saved r4 value |] 685 [| saved r3 value |] 686 [| saved r2 value |] 687 [| saved r1 value |] 688 [| saved r0 value |] 689 [| saved f7 value |] three words 690 [| saved f6 value |] three words 691 [| saved f5 value |] three words 692 [| saved f4 value |] three words 693 r0-r3 are not normally saved in a C function. */ 694 695 /* 1 for registers that have pervasive standard uses 696 and are not available for the register allocator. */ 697 #define FIXED_REGISTERS \ 698 { \ 699 0,0,0,0,0,0,0,0, \ 700 0,0,0,0,0,1,0,1, \ 701 0,0,0,0,0,0,0,0, \ 702 1,1,1, \ 703 1,1,1,1,1,1,1,1, \ 704 1,1,1,1,1,1,1,1, \ 705 1,1,1,1,1,1,1,1, \ 706 1,1,1,1,1,1,1,1, \ 707 1,1,1,1, \ 708 1,1,1,1,1,1,1,1, \ 709 1,1,1,1,1,1,1,1, \ 710 1,1,1,1,1,1,1,1, \ 711 1,1,1,1,1,1,1,1, \ 712 1,1,1,1,1,1,1,1, \ 713 1,1,1,1,1,1,1,1, \ 714 1,1,1,1,1,1,1,1, \ 715 1,1,1,1,1,1,1,1, \ 716 1 \ 717 } 718 719 /* 1 for registers not available across function calls. 720 These must include the FIXED_REGISTERS and also any 721 registers that can be used without being saved. 722 The latter must include the registers where values are returned 723 and the register where structure-value addresses are passed. 724 Aside from that, you can include as many other registers as you like. 725 The CC is not preserved over function calls on the ARM 6, so it is 726 easier to assume this for all. SFP is preserved, since FP is. */ 727 #define CALL_USED_REGISTERS \ 728 { \ 729 1,1,1,1,0,0,0,0, \ 730 0,0,0,0,1,1,1,1, \ 731 1,1,1,1,0,0,0,0, \ 732 1,1,1, \ 733 1,1,1,1,1,1,1,1, \ 734 1,1,1,1,1,1,1,1, \ 735 1,1,1,1,1,1,1,1, \ 736 1,1,1,1,1,1,1,1, \ 737 1,1,1,1, \ 738 1,1,1,1,1,1,1,1, \ 739 1,1,1,1,1,1,1,1, \ 740 1,1,1,1,1,1,1,1, \ 741 1,1,1,1,1,1,1,1, \ 742 1,1,1,1,1,1,1,1, \ 743 1,1,1,1,1,1,1,1, \ 744 1,1,1,1,1,1,1,1, \ 745 1,1,1,1,1,1,1,1, \ 746 1 \ 747 } 748 749 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 750 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 751 #endif 752 753 #define CONDITIONAL_REGISTER_USAGE \ 754 { \ 755 int regno; \ 756 \ 757 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \ 758 { \ 759 for (regno = FIRST_FPA_REGNUM; \ 760 regno <= LAST_FPA_REGNUM; ++regno) \ 761 fixed_regs[regno] = call_used_regs[regno] = 1; \ 762 } \ 763 \ 764 if (TARGET_THUMB && optimize_size) \ 765 { \ 766 /* When optimizing for size, it's better not to use \ 767 the HI regs, because of the overhead of stacking \ 768 them. */ \ 769 /* ??? Is this still true for thumb2? */ \ 770 for (regno = FIRST_HI_REGNUM; \ 771 regno <= LAST_HI_REGNUM; ++regno) \ 772 fixed_regs[regno] = call_used_regs[regno] = 1; \ 773 } \ 774 \ 775 /* The link register can be clobbered by any branch insn, \ 776 but we have no way to track that at present, so mark \ 777 it as unavailable. */ \ 778 if (TARGET_THUMB1) \ 779 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 780 \ 781 if (TARGET_32BIT && TARGET_HARD_FLOAT) \ 782 { \ 783 if (TARGET_MAVERICK) \ 784 { \ 785 for (regno = FIRST_FPA_REGNUM; \ 786 regno <= LAST_FPA_REGNUM; ++ regno) \ 787 fixed_regs[regno] = call_used_regs[regno] = 1; \ 788 for (regno = FIRST_CIRRUS_FP_REGNUM; \ 789 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 790 { \ 791 fixed_regs[regno] = 0; \ 792 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 793 } \ 794 } \ 795 if (TARGET_VFP) \ 796 { \ 797 /* VFPv3 registers are disabled when earlier VFP \ 798 versions are selected due to the definition of \ 799 LAST_VFP_REGNUM. */ \ 800 for (regno = FIRST_VFP_REGNUM; \ 801 regno <= LAST_VFP_REGNUM; ++ regno) \ 802 { \ 803 fixed_regs[regno] = 0; \ 804 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \ 805 || regno >= FIRST_VFP_REGNUM + 32; \ 806 } \ 807 } \ 808 } \ 809 \ 810 if (TARGET_REALLY_IWMMXT) \ 811 { \ 812 regno = FIRST_IWMMXT_GR_REGNUM; \ 813 /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 814 and wCG1 as call-preserved registers. The 2002/11/21 \ 815 revision changed this so that all wCG registers are \ 816 scratch registers. */ \ 817 for (regno = FIRST_IWMMXT_GR_REGNUM; \ 818 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 819 fixed_regs[regno] = 0; \ 820 /* The XScale ABI has wR0 - wR9 as scratch registers, \ 821 the rest as call-preserved registers. */ \ 822 for (regno = FIRST_IWMMXT_REGNUM; \ 823 regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 824 { \ 825 fixed_regs[regno] = 0; \ 826 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 827 } \ 828 } \ 829 \ 830 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 831 { \ 832 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 833 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 834 } \ 835 else if (TARGET_APCS_STACK) \ 836 { \ 837 fixed_regs[10] = 1; \ 838 call_used_regs[10] = 1; \ 839 } \ 840 /* -mcaller-super-interworking reserves r11 for calls to \ 841 _interwork_r11_call_via_rN(). Making the register global \ 842 is an easy way of ensuring that it remains valid for all \ 843 calls. */ \ 844 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \ 845 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \ 846 { \ 847 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 848 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 849 if (TARGET_CALLER_INTERWORKING) \ 850 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 851 } \ 852 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 853 } 854 855 /* These are a couple of extensions to the formats accepted 856 by asm_fprintf: 857 %@ prints out ASM_COMMENT_START 858 %r prints out REGISTER_PREFIX reg_names[arg] */ 859 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 860 case '@': \ 861 fputs (ASM_COMMENT_START, FILE); \ 862 break; \ 863 \ 864 case 'r': \ 865 fputs (REGISTER_PREFIX, FILE); \ 866 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 867 break; 868 869 /* Round X up to the nearest word. */ 870 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 871 872 /* Convert fron bytes to ints. */ 873 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 874 875 /* The number of (integer) registers required to hold a quantity of type MODE. 876 Also used for VFP registers. */ 877 #define ARM_NUM_REGS(MODE) \ 878 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 879 880 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 881 #define ARM_NUM_REGS2(MODE, TYPE) \ 882 ARM_NUM_INTS ((MODE) == BLKmode ? \ 883 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 884 885 /* The number of (integer) argument register available. */ 886 #define NUM_ARG_REGS 4 887 888 /* Return the register number of the N'th (integer) argument. */ 889 #define ARG_REGISTER(N) (N - 1) 890 891 /* Specify the registers used for certain standard purposes. 892 The values of these macros are register numbers. */ 893 894 /* The number of the last argument register. */ 895 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 896 897 /* The numbers of the Thumb register ranges. */ 898 #define FIRST_LO_REGNUM 0 899 #define LAST_LO_REGNUM 7 900 #define FIRST_HI_REGNUM 8 901 #define LAST_HI_REGNUM 11 902 903 #ifndef TARGET_UNWIND_INFO 904 /* We use sjlj exceptions for backwards compatibility. */ 905 #define MUST_USE_SJLJ_EXCEPTIONS 1 906 #endif 907 908 /* We can generate DWARF2 Unwind info, even though we don't use it. */ 909 #define DWARF2_UNWIND_INFO 1 910 911 /* Use r0 and r1 to pass exception handling information. */ 912 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 913 914 /* The register that holds the return address in exception handlers. */ 915 #define ARM_EH_STACKADJ_REGNUM 2 916 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 917 918 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 919 as an invisible last argument (possible since varargs don't exist in 920 Pascal), so the following is not true. */ 921 #define STATIC_CHAIN_REGNUM 12 922 923 /* Define this to be where the real frame pointer is if it is not possible to 924 work out the offset between the frame pointer and the automatic variables 925 until after register allocation has taken place. FRAME_POINTER_REGNUM 926 should point to a special register that we will make sure is eliminated. 927 928 For the Thumb we have another problem. The TPCS defines the frame pointer 929 as r11, and GCC believes that it is always possible to use the frame pointer 930 as base register for addressing purposes. (See comments in 931 find_reloads_address()). But - the Thumb does not allow high registers, 932 including r11, to be used as base address registers. Hence our problem. 933 934 The solution used here, and in the old thumb port is to use r7 instead of 935 r11 as the hard frame pointer and to have special code to generate 936 backtrace structures on the stack (if required to do so via a command line 937 option) using r11. This is the only 'user visible' use of r11 as a frame 938 pointer. */ 939 #define ARM_HARD_FRAME_POINTER_REGNUM 11 940 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 941 942 #define HARD_FRAME_POINTER_REGNUM \ 943 (TARGET_ARM \ 944 ? ARM_HARD_FRAME_POINTER_REGNUM \ 945 : THUMB_HARD_FRAME_POINTER_REGNUM) 946 947 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 948 949 /* Register to use for pushing function arguments. */ 950 #define STACK_POINTER_REGNUM SP_REGNUM 951 952 /* ARM floating pointer registers. */ 953 #define FIRST_FPA_REGNUM 16 954 #define LAST_FPA_REGNUM 23 955 #define IS_FPA_REGNUM(REGNUM) \ 956 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) 957 958 #define FIRST_IWMMXT_GR_REGNUM 43 959 #define LAST_IWMMXT_GR_REGNUM 46 960 #define FIRST_IWMMXT_REGNUM 47 961 #define LAST_IWMMXT_REGNUM 62 962 #define IS_IWMMXT_REGNUM(REGNUM) \ 963 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 964 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 965 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 966 967 /* Base register for access to local variables of the function. */ 968 #define FRAME_POINTER_REGNUM 25 969 970 /* Base register for access to arguments of the function. */ 971 #define ARG_POINTER_REGNUM 26 972 973 #define FIRST_CIRRUS_FP_REGNUM 27 974 #define LAST_CIRRUS_FP_REGNUM 42 975 #define IS_CIRRUS_REGNUM(REGNUM) \ 976 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 977 978 #define FIRST_VFP_REGNUM 63 979 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ 980 #define LAST_VFP_REGNUM \ 981 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 982 983 #define IS_VFP_REGNUM(REGNUM) \ 984 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 985 986 /* VFP registers are split into two types: those defined by VFP versions < 3 987 have D registers overlaid on consecutive pairs of S registers. VFP version 3 988 defines 16 new D registers (d16-d31) which, for simplicity and correctness 989 in various parts of the backend, we implement as "fake" single-precision 990 registers (which would be S32-S63, but cannot be used in that way). The 991 following macros define these ranges of registers. */ 992 #define LAST_LO_VFP_REGNUM 94 993 #define FIRST_HI_VFP_REGNUM 95 994 #define LAST_HI_VFP_REGNUM 126 995 996 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 997 ((REGNUM) <= LAST_LO_VFP_REGNUM) 998 999 /* DFmode values are only valid in even register pairs. */ 1000 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1001 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1002 1003 /* Neon Quad values must start at a multiple of four registers. */ 1004 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1005 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1006 1007 /* Neon structures of vectors must be in even register pairs and there 1008 must be enough registers available. Because of various patterns 1009 requiring quad registers, we require them to start at a multiple of 1010 four. */ 1011 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1012 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1013 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1014 1015 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1016 /* + 16 Cirrus registers take us up to 43. */ 1017 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1018 /* VFP (VFP3) adds 32 (64) + 1 more. */ 1019 #define FIRST_PSEUDO_REGISTER 128 1020 1021 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1022 1023 /* Value should be nonzero if functions must have frame pointers. 1024 Zero means the frame pointer need not be set up (and parms may be accessed 1025 via the stack pointer) in functions that seem suitable. 1026 If we have to have a frame pointer we might as well make use of it. 1027 APCS says that the frame pointer does not need to be pushed in leaf 1028 functions, or simple tail call functions. */ 1029 1030 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1031 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1032 #endif 1033 1034 #define FRAME_POINTER_REQUIRED \ 1035 (cfun->has_nonlocal_label \ 1036 || SUBTARGET_FRAME_POINTER_REQUIRED \ 1037 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) 1038 1039 /* Return number of consecutive hard regs needed starting at reg REGNO 1040 to hold something of mode MODE. 1041 This is ordinarily the length in words of a value of mode MODE 1042 but can be less for certain modes in special long registers. 1043 1044 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1045 mode. */ 1046 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1047 ((TARGET_32BIT \ 1048 && REGNO >= FIRST_FPA_REGNUM \ 1049 && REGNO != FRAME_POINTER_REGNUM \ 1050 && REGNO != ARG_POINTER_REGNUM) \ 1051 && !IS_VFP_REGNUM (REGNO) \ 1052 ? 1 : ARM_NUM_REGS (MODE)) 1053 1054 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1055 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1056 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1057 1058 /* Value is 1 if it is a good idea to tie two pseudo registers 1059 when one has mode MODE1 and one has mode MODE2. 1060 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1061 for any hard reg, then this must be 0 for correct output. */ 1062 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1063 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1064 1065 #define VALID_IWMMXT_REG_MODE(MODE) \ 1066 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1067 1068 /* Modes valid for Neon D registers. */ 1069 #define VALID_NEON_DREG_MODE(MODE) \ 1070 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1071 || (MODE) == V2SFmode || (MODE) == DImode) 1072 1073 /* Modes valid for Neon Q registers. */ 1074 #define VALID_NEON_QREG_MODE(MODE) \ 1075 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1076 || (MODE) == V4SFmode || (MODE) == V2DImode) 1077 1078 /* Structure modes valid for Neon registers. */ 1079 #define VALID_NEON_STRUCT_MODE(MODE) \ 1080 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1081 || (MODE) == CImode || (MODE) == XImode) 1082 1083 /* The order in which register should be allocated. It is good to use ip 1084 since no saving is required (though calls clobber it) and it never contains 1085 function parameters. It is quite good to use lr since other calls may 1086 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1087 least likely to contain a function parameter; in addition results are 1088 returned in r0. 1089 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1090 then D8-D15. The reason for doing this is to attempt to reduce register 1091 pressure when both single- and double-precision registers are used in a 1092 function. */ 1093 1094 #define REG_ALLOC_ORDER \ 1095 { \ 1096 3, 2, 1, 0, 12, 14, 4, 5, \ 1097 6, 7, 8, 10, 9, 11, 13, 15, \ 1098 16, 17, 18, 19, 20, 21, 22, 23, \ 1099 27, 28, 29, 30, 31, 32, 33, 34, \ 1100 35, 36, 37, 38, 39, 40, 41, 42, \ 1101 43, 44, 45, 46, 47, 48, 49, 50, \ 1102 51, 52, 53, 54, 55, 56, 57, 58, \ 1103 59, 60, 61, 62, \ 1104 24, 25, 26, \ 1105 95, 96, 97, 98, 99, 100, 101, 102, \ 1106 103, 104, 105, 106, 107, 108, 109, 110, \ 1107 111, 112, 113, 114, 115, 116, 117, 118, \ 1108 119, 120, 121, 122, 123, 124, 125, 126, \ 1109 78, 77, 76, 75, 74, 73, 72, 71, \ 1110 70, 69, 68, 67, 66, 65, 64, 63, \ 1111 79, 80, 81, 82, 83, 84, 85, 86, \ 1112 87, 88, 89, 90, 91, 92, 93, 94, \ 1113 127 \ 1114 } 1115 1116 /* Use different register alloc ordering for Thumb. */ 1117 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () 1118 1119 /* Interrupt functions can only use registers that have already been 1120 saved by the prologue, even if they would normally be 1121 call-clobbered. */ 1122 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1123 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1124 df_regs_ever_live_p (DST)) 1125 1126 /* Register and constant classes. */ 1128 1129 /* Register classes: used to be simple, just all ARM regs or all FPA regs 1130 Now that the Thumb is involved it has become more complicated. */ 1131 enum reg_class 1132 { 1133 NO_REGS, 1134 FPA_REGS, 1135 CIRRUS_REGS, 1136 VFP_D0_D7_REGS, 1137 VFP_LO_REGS, 1138 VFP_HI_REGS, 1139 VFP_REGS, 1140 IWMMXT_GR_REGS, 1141 IWMMXT_REGS, 1142 LO_REGS, 1143 STACK_REG, 1144 BASE_REGS, 1145 HI_REGS, 1146 CC_REG, 1147 VFPCC_REG, 1148 GENERAL_REGS, 1149 CORE_REGS, 1150 ALL_REGS, 1151 LIM_REG_CLASSES 1152 }; 1153 1154 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1155 1156 /* Give names of register classes as strings for dump file. */ 1157 #define REG_CLASS_NAMES \ 1158 { \ 1159 "NO_REGS", \ 1160 "FPA_REGS", \ 1161 "CIRRUS_REGS", \ 1162 "VFP_D0_D7_REGS", \ 1163 "VFP_LO_REGS", \ 1164 "VFP_HI_REGS", \ 1165 "VFP_REGS", \ 1166 "IWMMXT_GR_REGS", \ 1167 "IWMMXT_REGS", \ 1168 "LO_REGS", \ 1169 "STACK_REG", \ 1170 "BASE_REGS", \ 1171 "HI_REGS", \ 1172 "CC_REG", \ 1173 "VFPCC_REG", \ 1174 "GENERAL_REGS", \ 1175 "CORE_REGS", \ 1176 "ALL_REGS", \ 1177 } 1178 1179 /* Define which registers fit in which classes. 1180 This is an initializer for a vector of HARD_REG_SET 1181 of length N_REG_CLASSES. */ 1182 #define REG_CLASS_CONTENTS \ 1183 { \ 1184 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1185 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ 1186 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ 1187 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1188 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ 1189 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ 1190 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ 1191 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ 1192 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ 1193 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1194 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1195 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1196 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1197 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ 1198 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ 1199 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1200 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1201 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1202 } 1203 1204 /* Any of the VFP register classes. */ 1205 #define IS_VFP_CLASS(X) \ 1206 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1207 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1208 1209 /* The same information, inverted: 1210 Return the class number of the smallest class containing 1211 reg number REGNO. This could be a conditional expression 1212 or could index an array. */ 1213 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1214 1215 /* The following macro defines cover classes for Integrated Register 1216 Allocator. Cover classes is a set of non-intersected register 1217 classes covering all hard registers used for register allocation 1218 purpose. Any move between two registers of a cover class should be 1219 cheaper than load or store of the registers. The macro value is 1220 array of register classes with LIM_REG_CLASSES used as the end 1221 marker. */ 1222 1223 #define IRA_COVER_CLASSES \ 1224 { \ 1225 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ 1226 LIM_REG_CLASSES \ 1227 } 1228 1229 /* FPA registers can't do subreg as all values are reformatted to internal 1230 precision. VFP registers may only be accessed in the mode they 1231 were set. */ 1232 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1233 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1234 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ 1235 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ 1236 : 0) 1237 1238 /* We need to define this for LO_REGS on thumb. Otherwise we can end up 1239 using r0-r4 for function arguments, r7 for the stack frame and don't 1240 have enough left over to do doubleword arithmetic. */ 1241 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1242 ((TARGET_THUMB && (CLASS) == LO_REGS) \ 1243 || (CLASS) == CC_REG) 1244 1245 /* The class value for index registers, and the one for base regs. */ 1246 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1247 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1248 1249 /* For the Thumb the high registers cannot be used as base registers 1250 when addressing quantities in QI or HI mode; if we don't know the 1251 mode, then we must be conservative. */ 1252 #define MODE_BASE_REG_CLASS(MODE) \ 1253 (TARGET_32BIT ? CORE_REGS : \ 1254 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1255 1256 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1257 instead of BASE_REGS. */ 1258 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1259 1260 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1261 registers explicitly used in the rtl to be used as spill registers 1262 but prevents the compiler from extending the lifetime of these 1263 registers. */ 1264 #define SMALL_REGISTER_CLASSES TARGET_THUMB1 1265 1266 /* Given an rtx X being reloaded into a reg required to be 1267 in class CLASS, return the class of reg to actually use. 1268 In general this is just CLASS, but for the Thumb core registers and 1269 immediate constants we prefer a LO_REGS class or a subset. */ 1270 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1271 (TARGET_ARM ? (CLASS) : \ 1272 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ 1273 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ 1274 ? LO_REGS : (CLASS))) 1275 1276 /* Must leave BASE_REGS reloads alone */ 1277 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1278 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1279 ? ((true_regnum (X) == -1 ? LO_REGS \ 1280 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1281 : NO_REGS)) \ 1282 : NO_REGS) 1283 1284 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1285 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1286 ? ((true_regnum (X) == -1 ? LO_REGS \ 1287 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1288 : NO_REGS)) \ 1289 : NO_REGS) 1290 1291 /* Return the register class of a scratch register needed to copy IN into 1292 or out of a register in CLASS in MODE. If it can be done directly, 1293 NO_REGS is returned. */ 1294 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1295 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1296 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1297 && IS_VFP_CLASS (CLASS)) \ 1298 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1299 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1300 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1301 : TARGET_32BIT \ 1302 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1303 ? GENERAL_REGS : NO_REGS) \ 1304 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1305 1306 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1307 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1308 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1309 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1310 && IS_VFP_CLASS (CLASS)) \ 1311 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1312 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1313 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1314 /* Cannot load constants into Cirrus registers. */ \ 1315 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ 1316 && (CLASS) == CIRRUS_REGS \ 1317 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1318 ? GENERAL_REGS : \ 1319 (TARGET_32BIT ? \ 1320 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1321 && CONSTANT_P (X)) \ 1322 ? GENERAL_REGS : \ 1323 (((MODE) == HImode && ! arm_arch4 \ 1324 && (GET_CODE (X) == MEM \ 1325 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1326 && true_regnum (X) == -1))) \ 1327 ? GENERAL_REGS : NO_REGS) \ 1328 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1329 1330 /* Try a machine-dependent way of reloading an illegitimate address 1331 operand. If we find one, push the reload and jump to WIN. This 1332 macro is used in only one place: `find_reloads_address' in reload.c. 1333 1334 For the ARM, we wish to handle large displacements off a base 1335 register by splitting the addend across a MOV and the mem insn. 1336 This can cut the number of reloads needed. */ 1337 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1338 do \ 1339 { \ 1340 if (GET_CODE (X) == PLUS \ 1341 && GET_CODE (XEXP (X, 0)) == REG \ 1342 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1343 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1344 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1345 { \ 1346 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1347 HOST_WIDE_INT low, high; \ 1348 \ 1349 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ 1350 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1351 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ 1352 /* Need to be careful, -256 is not a valid offset. */ \ 1353 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1354 else if (MODE == SImode \ 1355 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1356 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1357 /* Need to be careful, -4096 is not a valid offset. */ \ 1358 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1359 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1360 /* Need to be careful, -256 is not a valid offset. */ \ 1361 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1362 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1363 && TARGET_HARD_FLOAT && TARGET_FPA) \ 1364 /* Need to be careful, -1024 is not a valid offset. */ \ 1365 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1366 else \ 1367 break; \ 1368 \ 1369 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1370 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1371 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1372 /* Check for overflow or zero */ \ 1373 if (low == 0 || high == 0 || (high + low != val)) \ 1374 break; \ 1375 \ 1376 /* Reload the high part into a base reg; leave the low part \ 1377 in the mem. */ \ 1378 X = gen_rtx_PLUS (GET_MODE (X), \ 1379 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1380 GEN_INT (high)), \ 1381 GEN_INT (low)); \ 1382 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1383 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1384 VOIDmode, 0, 0, OPNUM, TYPE); \ 1385 goto WIN; \ 1386 } \ 1387 } \ 1388 while (0) 1389 1390 /* XXX If an HImode FP+large_offset address is converted to an HImode 1391 SP+large_offset address, then reload won't know how to fix it. It sees 1392 only that SP isn't valid for HImode, and so reloads the SP into an index 1393 register, but the resulting address is still invalid because the offset 1394 is too big. We fix it here instead by reloading the entire address. */ 1395 /* We could probably achieve better results by defining PROMOTE_MODE to help 1396 cope with the variances between the Thumb's signed and unsigned byte and 1397 halfword load instructions. */ 1398 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1399 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1400 do { \ 1401 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1402 if (new_x) \ 1403 { \ 1404 X = new_x; \ 1405 goto WIN; \ 1406 } \ 1407 } while (0) 1408 1409 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1410 if (TARGET_ARM) \ 1411 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1412 else \ 1413 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1414 1415 /* Return the maximum number of consecutive registers 1416 needed to represent mode MODE in a register of class CLASS. 1417 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1418 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1419 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1420 1421 /* If defined, gives a class of registers that cannot be used as the 1422 operand of a SUBREG that changes the mode of the object illegally. */ 1423 1424 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */ 1425 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1426 (TARGET_32BIT ? \ 1427 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1428 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1429 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \ 1430 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \ 1431 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1432 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1433 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1434 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1435 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1436 2) \ 1437 : \ 1438 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1439 1440 /* Stack layout; function entry, exit and calling. */ 1442 1443 /* Define this if pushing a word on the stack 1444 makes the stack pointer a smaller address. */ 1445 #define STACK_GROWS_DOWNWARD 1 1446 1447 /* Define this to nonzero if the nominal address of the stack frame 1448 is at the high-address end of the local variables; 1449 that is, each additional local variable allocated 1450 goes at a more negative offset in the frame. */ 1451 #define FRAME_GROWS_DOWNWARD 1 1452 1453 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1454 When present, it is one word in size, and sits at the top of the frame, 1455 between the soft frame pointer and either r7 or r11. 1456 1457 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1458 and only then if some outgoing arguments are passed on the stack. It would 1459 be tempting to also check whether the stack arguments are passed by indirect 1460 calls, but there seems to be no reason in principle why a post-reload pass 1461 couldn't convert a direct call into an indirect one. */ 1462 #define CALLER_INTERWORKING_SLOT_SIZE \ 1463 (TARGET_CALLER_INTERWORKING \ 1464 && crtl->outgoing_args_size != 0 \ 1465 ? UNITS_PER_WORD : 0) 1466 1467 /* Offset within stack frame to start allocating local variables at. 1468 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1469 first local allocated. Otherwise, it is the offset to the BEGINNING 1470 of the first local allocated. */ 1471 #define STARTING_FRAME_OFFSET 0 1472 1473 /* If we generate an insn to push BYTES bytes, 1474 this says how many the stack pointer really advances by. */ 1475 /* The push insns do not do this rounding implicitly. 1476 So don't define this. */ 1477 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1478 1479 /* Define this if the maximum size of all the outgoing args is to be 1480 accumulated and pushed during the prologue. The amount can be 1481 found in the variable crtl->outgoing_args_size. */ 1482 #define ACCUMULATE_OUTGOING_ARGS 1 1483 1484 /* Offset of first parameter from the argument pointer register value. */ 1485 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1486 1487 /* Value is the number of byte of arguments automatically 1488 popped when returning from a subroutine call. 1489 FUNDECL is the declaration node of the function (as a tree), 1490 FUNTYPE is the data type of the function (as a tree), 1491 or for a library call it is an identifier node for the subroutine name. 1492 SIZE is the number of bytes of arguments passed on the stack. 1493 1494 On the ARM, the caller does not pop any of its arguments that were passed 1495 on the stack. */ 1496 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1497 1498 /* Define how to find the value returned by a library function 1499 assuming the value has mode MODE. */ 1500 #define LIBCALL_VALUE(MODE) \ 1501 (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ 1502 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1503 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ 1504 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ 1505 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1506 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1507 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ 1508 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1509 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1510 1511 /* Define how to find the value returned by a function. 1512 VALTYPE is the data type of the value (as a tree). 1513 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1514 otherwise, FUNC is 0. */ 1515 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1516 arm_function_value (VALTYPE, FUNC); 1517 1518 /* 1 if N is a possible register number for a function value. 1519 On the ARM, only r0 and f0 can return results. */ 1520 /* On a Cirrus chip, mvf0 can return results. */ 1521 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1522 ((REGNO) == ARG_REGISTER (1) \ 1523 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ 1524 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ 1525 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ 1526 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ 1527 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) 1528 1529 /* Amount of memory needed for an untyped call to save all possible return 1530 registers. */ 1531 #define APPLY_RESULT_SIZE arm_apply_result_size() 1532 1533 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1534 values must be in memory. On the ARM, they need only do so if larger 1535 than a word, or if they contain elements offset from zero in the struct. */ 1536 #define DEFAULT_PCC_STRUCT_RETURN 0 1537 1538 /* These bits describe the different types of function supported 1539 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1540 normal function and an interworked function, for example. Knowing the 1541 type of a function is important for determining its prologue and 1542 epilogue sequences. 1543 Note value 7 is currently unassigned. Also note that the interrupt 1544 function types all have bit 2 set, so that they can be tested for easily. 1545 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1546 machine_function structure is initialized (to zero) func_type will 1547 default to unknown. This will force the first use of arm_current_func_type 1548 to call arm_compute_func_type. */ 1549 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1550 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1551 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1552 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1553 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1554 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1555 1556 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1557 1558 /* In addition functions can have several type modifiers, 1559 outlined by these bit masks: */ 1560 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1561 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1562 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1563 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1564 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1565 1566 /* Some macros to test these flags. */ 1567 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1568 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1569 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1570 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1571 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1572 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1573 1574 1575 /* Structure used to hold the function stack frame layout. Offsets are 1576 relative to the stack pointer on function entry. Positive offsets are 1577 in the direction of stack growth. 1578 Only soft_frame is used in thumb mode. */ 1579 1580 typedef struct arm_stack_offsets GTY(()) 1581 { 1582 int saved_args; /* ARG_POINTER_REGNUM. */ 1583 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1584 int saved_regs; 1585 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1586 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1587 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1588 unsigned int saved_regs_mask; 1589 } 1590 arm_stack_offsets; 1591 1592 /* A C structure for machine-specific, per-function data. 1593 This is added to the cfun structure. */ 1594 typedef struct machine_function GTY(()) 1595 { 1596 /* Additional stack adjustment in __builtin_eh_throw. */ 1597 rtx eh_epilogue_sp_ofs; 1598 /* Records if LR has to be saved for far jumps. */ 1599 int far_jump_used; 1600 /* Records if ARG_POINTER was ever live. */ 1601 int arg_pointer_live; 1602 /* Records if the save of LR has been eliminated. */ 1603 int lr_save_eliminated; 1604 /* The size of the stack frame. Only valid after reload. */ 1605 arm_stack_offsets stack_offsets; 1606 /* Records the type of the current function. */ 1607 unsigned long func_type; 1608 /* Record if the function has a variable argument list. */ 1609 int uses_anonymous_args; 1610 /* Records if sibcalls are blocked because an argument 1611 register is needed to preserve stack alignment. */ 1612 int sibcall_blocked; 1613 /* The PIC register for this function. This might be a pseudo. */ 1614 rtx pic_reg; 1615 /* Labels for per-function Thumb call-via stubs. One per potential calling 1616 register. We can never call via LR or PC. We can call via SP if a 1617 trampoline happens to be on the top of the stack. */ 1618 rtx call_via[14]; 1619 } 1620 machine_function; 1621 1622 /* As in the machine_function, a global set of call-via labels, for code 1623 that is in text_section. */ 1624 extern GTY(()) rtx thumb_call_via_label[14]; 1625 1626 /* A C type for declaring a variable that is used as the first argument of 1627 `FUNCTION_ARG' and other related values. For some target machines, the 1628 type `int' suffices and can hold the number of bytes of argument so far. */ 1629 typedef struct 1630 { 1631 /* This is the number of registers of arguments scanned so far. */ 1632 int nregs; 1633 /* This is the number of iWMMXt register arguments scanned so far. */ 1634 int iwmmxt_nregs; 1635 int named_count; 1636 int nargs; 1637 int can_split; 1638 } CUMULATIVE_ARGS; 1639 1640 /* Define where to put the arguments to a function. 1641 Value is zero to push the argument on the stack, 1642 or a hard register in which to store the argument. 1643 1644 MODE is the argument's machine mode. 1645 TYPE is the data type of the argument (as a tree). 1646 This is null for libcalls where that information may 1647 not be available. 1648 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1649 the preceding args and about the function being called. 1650 NAMED is nonzero if this argument is a named parameter 1651 (otherwise it is an extra parameter matching an ellipsis). 1652 1653 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1654 other arguments are passed on the stack. If (NAMED == 0) (which happens 1655 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is 1656 defined), say it is passed in the stack (function_prologue will 1657 indeed make it pass in the stack if necessary). */ 1658 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1659 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1660 1661 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1662 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1663 1664 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1665 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1666 1667 /* For AAPCS, padding should never be below the argument. For other ABIs, 1668 * mimic the default. */ 1669 #define PAD_VARARGS_DOWN \ 1670 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1671 1672 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1673 for a call to a function whose data type is FNTYPE. 1674 For a library call, FNTYPE is 0. 1675 On the ARM, the offset starts at 0. */ 1676 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1677 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1678 1679 /* Update the data in CUM to advance over an argument 1680 of mode MODE and data type TYPE. 1681 (TYPE is null for libcalls where that information may not be available.) */ 1682 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1683 (CUM).nargs += 1; \ 1684 if (arm_vector_mode_supported_p (MODE) \ 1685 && (CUM).named_count > (CUM).nargs \ 1686 && TARGET_IWMMXT_ABI) \ 1687 (CUM).iwmmxt_nregs += 1; \ 1688 else \ 1689 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) 1690 1691 /* If defined, a C expression that gives the alignment boundary, in bits, of an 1692 argument with the specified mode and type. If it is not defined, 1693 `PARM_BOUNDARY' is used for all arguments. */ 1694 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1695 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \ 1696 ? DOUBLEWORD_ALIGNMENT \ 1697 : PARM_BOUNDARY ) 1698 1699 /* 1 if N is a possible register number for function argument passing. 1700 On the ARM, r0-r3 are used to pass args. */ 1701 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1702 (IN_RANGE ((REGNO), 0, 3) \ 1703 || (TARGET_IWMMXT_ABI \ 1704 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1705 1706 1707 /* If your target environment doesn't prefix user functions with an 1709 underscore, you may wish to re-define this to prevent any conflicts. */ 1710 #ifndef ARM_MCOUNT_NAME 1711 #define ARM_MCOUNT_NAME "*mcount" 1712 #endif 1713 1714 /* Call the function profiler with a given profile label. The Acorn 1715 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1716 On the ARM the full profile code will look like: 1717 .data 1718 LP1 1719 .word 0 1720 .text 1721 mov ip, lr 1722 bl mcount 1723 .word LP1 1724 1725 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1726 will output the .text section. 1727 1728 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1729 ``prof'' doesn't seem to mind about this! 1730 1731 Note - this version of the code is designed to work in both ARM and 1732 Thumb modes. */ 1733 #ifndef ARM_FUNCTION_PROFILER 1734 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1735 { \ 1736 char temp[20]; \ 1737 rtx sym; \ 1738 \ 1739 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1740 IP_REGNUM, LR_REGNUM); \ 1741 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1742 fputc ('\n', STREAM); \ 1743 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1744 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1745 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1746 } 1747 #endif 1748 1749 #ifdef THUMB_FUNCTION_PROFILER 1750 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1751 if (TARGET_ARM) \ 1752 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1753 else \ 1754 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1755 #else 1756 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1757 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1758 #endif 1759 1760 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1761 the stack pointer does not matter. The value is tested only in 1762 functions that have frame pointers. 1763 No definition is equivalent to always zero. 1764 1765 On the ARM, the function epilogue recovers the stack pointer from the 1766 frame. */ 1767 #define EXIT_IGNORE_STACK 1 1768 1769 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1770 1771 /* Determine if the epilogue should be output as RTL. 1772 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1773 /* This is disabled for Thumb-2 because it will confuse the 1774 conditional insn counter. */ 1775 #define USE_RETURN_INSN(ISCOND) \ 1776 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 1777 1778 /* Definitions for register eliminations. 1779 1780 This is an array of structures. Each structure initializes one pair 1781 of eliminable registers. The "from" register number is given first, 1782 followed by "to". Eliminations of the same "from" register are listed 1783 in order of preference. 1784 1785 We have two registers that can be eliminated on the ARM. First, the 1786 arg pointer register can often be eliminated in favor of the stack 1787 pointer register. Secondly, the pseudo frame pointer register can always 1788 be eliminated; it is replaced with either the stack or the real frame 1789 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1790 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1791 1792 #define ELIMINABLE_REGS \ 1793 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1794 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1795 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1796 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1797 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1798 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1799 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1800 1801 /* Given FROM and TO register numbers, say whether this elimination is 1802 allowed. Frame pointer elimination is automatically handled. 1803 1804 All eliminations are permissible. Note that ARG_POINTER_REGNUM and 1805 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 1806 pointer, we must eliminate FRAME_POINTER_REGNUM into 1807 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or 1808 ARG_POINTER_REGNUM. */ 1809 #define CAN_ELIMINATE(FROM, TO) \ 1810 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ 1811 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ 1812 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ 1813 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ 1814 1) 1815 1816 /* Define the offset between two registers, one to be eliminated, and the 1817 other its replacement, at the start of a routine. */ 1818 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1819 if (TARGET_ARM) \ 1820 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1821 else \ 1822 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1823 1824 /* Special case handling of the location of arguments passed on the stack. */ 1825 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1826 1827 /* Initialize data used by insn expanders. This is called from insn_emit, 1828 once for every function before code is generated. */ 1829 #define INIT_EXPANDERS arm_init_expanders () 1830 1831 /* Output assembler code for a block containing the constant parts 1832 of a trampoline, leaving space for the variable parts. 1833 1834 On the ARM, (if r8 is the static chain regnum, and remembering that 1835 referencing pc adds an offset of 8) the trampoline looks like: 1836 ldr r8, [pc, #0] 1837 ldr pc, [pc] 1838 .word static chain value 1839 .word function's address 1840 XXX FIXME: When the trampoline returns, r8 will be clobbered. */ 1841 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ 1842 { \ 1843 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1844 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 1845 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1846 PC_REGNUM, PC_REGNUM); \ 1847 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1848 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1849 } 1850 1851 /* The Thumb-2 trampoline is similar to the arm implementation. 1852 Unlike 16-bit Thumb, we enter the stub in thumb mode. */ 1853 #define THUMB2_TRAMPOLINE_TEMPLATE(FILE) \ 1854 { \ 1855 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \ 1856 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 1857 asm_fprintf (FILE, "\tldr.w\t%r, [%r, #4]\n", \ 1858 PC_REGNUM, PC_REGNUM); \ 1859 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1860 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1861 } 1862 1863 #define THUMB1_TRAMPOLINE_TEMPLATE(FILE) \ 1864 { \ 1865 ASM_OUTPUT_ALIGN(FILE, 2); \ 1866 fprintf (FILE, "\t.code\t16\n"); \ 1867 fprintf (FILE, ".Ltrampoline_start:\n"); \ 1868 asm_fprintf (FILE, "\tpush\t{r0, r1}\n"); \ 1869 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \ 1870 PC_REGNUM); \ 1871 asm_fprintf (FILE, "\tmov\t%r, r0\n", \ 1872 STATIC_CHAIN_REGNUM); \ 1873 asm_fprintf (FILE, "\tldr\tr0, [%r, #8]\n", \ 1874 PC_REGNUM); \ 1875 asm_fprintf (FILE, "\tstr\tr0, [%r, #4]\n", \ 1876 SP_REGNUM); \ 1877 asm_fprintf (FILE, "\tpop\t{r0, %r}\n", \ 1878 PC_REGNUM); \ 1879 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1880 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1881 } 1882 1883 #define TRAMPOLINE_TEMPLATE(FILE) \ 1884 if (TARGET_ARM) \ 1885 ARM_TRAMPOLINE_TEMPLATE (FILE) \ 1886 else if (TARGET_THUMB2) \ 1887 THUMB2_TRAMPOLINE_TEMPLATE (FILE) \ 1888 else \ 1889 THUMB1_TRAMPOLINE_TEMPLATE (FILE) 1890 1891 /* Thumb trampolines should be entered in thumb mode, so set the bottom bit 1892 of the address. */ 1893 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) do \ 1894 { \ 1895 if (TARGET_THUMB) \ 1896 (ADDR) = expand_simple_binop (Pmode, IOR, (ADDR), GEN_INT(1), \ 1897 gen_reg_rtx (Pmode), 0, OPTAB_LIB_WIDEN); \ 1898 } while(0) 1899 1900 /* Length in units of the trampoline for entering a nested function. */ 1901 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1902 1903 /* Alignment required for a trampoline in bits. */ 1904 #define TRAMPOLINE_ALIGNMENT 32 1905 1906 1907 /* Emit RTL insns to initialize the variable parts of a trampoline. 1908 FNADDR is an RTX for the address of the function's pure code. 1909 CXT is an RTX for the static chain value for the function. */ 1910 #ifndef INITIALIZE_TRAMPOLINE 1911 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1912 { \ 1913 emit_move_insn (gen_rtx_MEM (SImode, \ 1914 plus_constant (TRAMP, \ 1915 TARGET_32BIT ? 8 : 12)), \ 1916 CXT); \ 1917 emit_move_insn (gen_rtx_MEM (SImode, \ 1918 plus_constant (TRAMP, \ 1919 TARGET_32BIT ? 12 : 16)), \ 1920 FNADDR); \ 1921 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"), \ 1922 0, VOIDmode, 2, TRAMP, Pmode, \ 1923 plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode); \ 1924 } 1925 #endif 1926 1927 1928 /* Addressing modes, and classification of registers for them. */ 1930 #define HAVE_POST_INCREMENT 1 1931 #define HAVE_PRE_INCREMENT TARGET_32BIT 1932 #define HAVE_POST_DECREMENT TARGET_32BIT 1933 #define HAVE_PRE_DECREMENT TARGET_32BIT 1934 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1935 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1936 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1937 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1938 1939 /* Macros to check register numbers against specific register classes. */ 1940 1941 /* These assume that REGNO is a hard or pseudo reg number. 1942 They give nonzero only if REGNO is a hard reg of the suitable class 1943 or a pseudo reg currently allocated to a suitable hard reg. 1944 Since they use reg_renumber, they are safe only once reg_renumber 1945 has been allocated, which happens in local-alloc.c. */ 1946 #define TEST_REGNO(R, TEST, VALUE) \ 1947 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1948 1949 /* Don't allow the pc to be used. */ 1950 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1951 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1952 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1953 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1954 1955 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1956 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1957 || (GET_MODE_SIZE (MODE) >= 4 \ 1958 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1959 1960 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1961 (TARGET_THUMB1 \ 1962 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1963 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1964 1965 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1966 For Thumb, we can not use SP + reg, so reject SP. */ 1967 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1968 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1969 1970 /* For ARM code, we don't care about the mode, but for Thumb, the index 1971 must be suitable for use in a QImode load. */ 1972 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1973 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1974 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1975 1976 /* Maximum number of registers that can appear in a valid memory address. 1977 Shifts in addresses can't be by a register. */ 1978 #define MAX_REGS_PER_ADDRESS 2 1979 1980 /* Recognize any constant value that is a valid address. */ 1981 /* XXX We can address any constant, eventually... */ 1982 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1983 #define CONSTANT_ADDRESS_P(X) \ 1984 (GET_CODE (X) == SYMBOL_REF \ 1985 && (CONSTANT_POOL_ADDRESS_P (X) \ 1986 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1987 1988 /* True if SYMBOL + OFFSET constants must refer to something within 1989 SYMBOL's section. */ 1990 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1991 1992 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1993 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1994 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1995 #endif 1996 1997 /* Nonzero if the constant value X is a legitimate general operand. 1998 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1999 2000 On the ARM, allow any integer (invalid ones are removed later by insn 2001 patterns), nice doubles and symbol_refs which refer to the function's 2002 constant pool XXX. 2003 2004 When generating pic allow anything. */ 2005 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 2006 2007 #define THUMB_LEGITIMATE_CONSTANT_P(X) \ 2008 ( GET_CODE (X) == CONST_INT \ 2009 || GET_CODE (X) == CONST_DOUBLE \ 2010 || CONSTANT_ADDRESS_P (X) \ 2011 || flag_pic) 2012 2013 #define LEGITIMATE_CONSTANT_P(X) \ 2014 (!arm_cannot_force_const_mem (X) \ 2015 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ 2016 : THUMB_LEGITIMATE_CONSTANT_P (X))) 2017 2018 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 2019 #define SUBTARGET_NAME_ENCODING_LENGTHS 2020 #endif 2021 2022 /* This is a C fragment for the inside of a switch statement. 2023 Each case label should return the number of characters to 2024 be stripped from the start of a function's name, if that 2025 name starts with the indicated character. */ 2026 #define ARM_NAME_ENCODING_LENGTHS \ 2027 case '*': return 1; \ 2028 SUBTARGET_NAME_ENCODING_LENGTHS 2029 2030 /* This is how to output a reference to a user-level label named NAME. 2031 `assemble_name' uses this. */ 2032 #undef ASM_OUTPUT_LABELREF 2033 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 2034 arm_asm_output_labelref (FILE, NAME) 2035 2036 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 2037 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2038 if (TARGET_THUMB2) \ 2039 thumb2_asm_output_opcode (STREAM); 2040 2041 /* The EABI specifies that constructors should go in .init_array. 2042 Other targets use .ctors for compatibility. */ 2043 #ifndef ARM_EABI_CTORS_SECTION_OP 2044 #define ARM_EABI_CTORS_SECTION_OP \ 2045 "\t.section\t.init_array,\"aw\",%init_array" 2046 #endif 2047 #ifndef ARM_EABI_DTORS_SECTION_OP 2048 #define ARM_EABI_DTORS_SECTION_OP \ 2049 "\t.section\t.fini_array,\"aw\",%fini_array" 2050 #endif 2051 #define ARM_CTORS_SECTION_OP \ 2052 "\t.section\t.ctors,\"aw\",%progbits" 2053 #define ARM_DTORS_SECTION_OP \ 2054 "\t.section\t.dtors,\"aw\",%progbits" 2055 2056 /* Define CTORS_SECTION_ASM_OP. */ 2057 #undef CTORS_SECTION_ASM_OP 2058 #undef DTORS_SECTION_ASM_OP 2059 #ifndef IN_LIBGCC2 2060 # define CTORS_SECTION_ASM_OP \ 2061 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 2062 # define DTORS_SECTION_ASM_OP \ 2063 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 2064 #else /* !defined (IN_LIBGCC2) */ 2065 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 2066 so we cannot use the definition above. */ 2067 # ifdef __ARM_EABI__ 2068 /* The .ctors section is not part of the EABI, so we do not define 2069 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 2070 from trying to use it. We do define it when doing normal 2071 compilation, as .init_array can be used instead of .ctors. */ 2072 /* There is no need to emit begin or end markers when using 2073 init_array; the dynamic linker will compute the size of the 2074 array itself based on special symbols created by the static 2075 linker. However, we do need to arrange to set up 2076 exception-handling here. */ 2077 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 2078 # define CTOR_LIST_END /* empty */ 2079 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 2080 # define DTOR_LIST_END /* empty */ 2081 # else /* !defined (__ARM_EABI__) */ 2082 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 2083 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 2084 # endif /* !defined (__ARM_EABI__) */ 2085 #endif /* !defined (IN_LIBCC2) */ 2086 2087 /* True if the operating system can merge entities with vague linkage 2088 (e.g., symbols in COMDAT group) during dynamic linking. */ 2089 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 2090 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 2091 #endif 2092 2093 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 2094 2095 #ifdef TARGET_UNWIND_INFO 2096 #define ARM_EABI_UNWIND_TABLES \ 2097 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) 2098 #else 2099 #define ARM_EABI_UNWIND_TABLES 0 2100 #endif 2101 2102 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2103 and check its validity for a certain class. 2104 We have two alternate definitions for each of them. 2105 The usual definition accepts all pseudo regs; the other rejects 2106 them unless they have been allocated suitable hard regs. 2107 The symbol REG_OK_STRICT causes the latter definition to be used. 2108 Thumb-2 has the same restrictions as arm. */ 2109 #ifndef REG_OK_STRICT 2110 2111 #define ARM_REG_OK_FOR_BASE_P(X) \ 2112 (REGNO (X) <= LAST_ARM_REGNUM \ 2113 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2114 || REGNO (X) == FRAME_POINTER_REGNUM \ 2115 || REGNO (X) == ARG_POINTER_REGNUM) 2116 2117 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2118 ((REGNO (X) <= LAST_ARM_REGNUM \ 2119 && REGNO (X) != STACK_POINTER_REGNUM) \ 2120 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2121 || REGNO (X) == FRAME_POINTER_REGNUM \ 2122 || REGNO (X) == ARG_POINTER_REGNUM) 2123 2124 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2125 (REGNO (X) <= LAST_LO_REGNUM \ 2126 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2127 || (GET_MODE_SIZE (MODE) >= 4 \ 2128 && (REGNO (X) == STACK_POINTER_REGNUM \ 2129 || (X) == hard_frame_pointer_rtx \ 2130 || (X) == arg_pointer_rtx))) 2131 2132 #define REG_STRICT_P 0 2133 2134 #else /* REG_OK_STRICT */ 2135 2136 #define ARM_REG_OK_FOR_BASE_P(X) \ 2137 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2138 2139 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2140 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2141 2142 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2143 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2144 2145 #define REG_STRICT_P 1 2146 2147 #endif /* REG_OK_STRICT */ 2148 2149 /* Now define some helpers in terms of the above. */ 2150 2151 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2152 (TARGET_THUMB1 \ 2153 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2154 : ARM_REG_OK_FOR_BASE_P (X)) 2155 2156 /* For 16-bit Thumb, a valid index register is anything that can be used in 2157 a byte load instruction. */ 2158 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2159 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2160 2161 /* Nonzero if X is a hard reg that can be used as an index 2162 or if it is a pseudo reg. On the Thumb, the stack pointer 2163 is not suitable. */ 2164 #define REG_OK_FOR_INDEX_P(X) \ 2165 (TARGET_THUMB1 \ 2166 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2167 : ARM_REG_OK_FOR_INDEX_P (X)) 2168 2169 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2170 For Thumb, we can not use SP + reg, so reject SP. */ 2171 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2172 REG_OK_FOR_INDEX_P (X) 2173 2174 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2176 that is a valid memory address for an instruction. 2177 The MODE argument is the machine mode for the MEM expression 2178 that wants to use this address. */ 2179 2180 #define ARM_BASE_REGISTER_RTX_P(X) \ 2181 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 2182 2183 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2184 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 2185 2186 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2187 { \ 2188 if (arm_legitimate_address_p (MODE, X, SET, REG_STRICT_P)) \ 2189 goto WIN; \ 2190 } 2191 2192 #define THUMB2_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2193 { \ 2194 if (thumb2_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2195 goto WIN; \ 2196 } 2197 2198 #define THUMB1_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2199 { \ 2200 if (thumb1_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2201 goto WIN; \ 2202 } 2203 2204 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 2205 if (TARGET_ARM) \ 2206 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ 2207 else if (TARGET_THUMB2) \ 2208 THUMB2_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ 2209 else /* if (TARGET_THUMB1) */ \ 2210 THUMB1_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) 2211 2212 2213 /* Try machine-dependent ways of modifying an illegitimate address 2215 to be legitimate. If we find one, return the new, valid address. */ 2216 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2217 do { \ 2218 X = arm_legitimize_address (X, OLDX, MODE); \ 2219 } while (0) 2220 2221 /* ??? Implement LEGITIMIZE_ADDRESS for thumb2. */ 2222 #define THUMB2_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2223 do { \ 2224 } while (0) 2225 2226 #define THUMB1_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2227 do { \ 2228 X = thumb_legitimize_address (X, OLDX, MODE); \ 2229 } while (0) 2230 2231 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2232 do { \ 2233 if (TARGET_ARM) \ 2234 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2235 else if (TARGET_THUMB2) \ 2236 THUMB2_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2237 else \ 2238 THUMB1_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2239 \ 2240 if (memory_address_p (MODE, X)) \ 2241 goto WIN; \ 2242 } while (0) 2243 2244 /* Go to LABEL if ADDR (a legitimate address expression) 2245 has an effect that depends on the machine mode it is used for. */ 2246 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2247 { \ 2248 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 2249 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 2250 goto LABEL; \ 2251 } 2252 2253 /* Nothing helpful to do for the Thumb */ 2254 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2255 if (TARGET_32BIT) \ 2256 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) 2257 2258 /* Define this so we can compile MS code for use with WINE. */ 2259 #define HANDLE_PRAGMA_PACK_PUSH_POP 2260 2261 /* Specify the machine mode that this machine uses 2262 for the index in the tablejump instruction. */ 2263 #define CASE_VECTOR_MODE Pmode 2264 2265 #define CASE_VECTOR_PC_RELATIVE TARGET_THUMB2 2266 2267 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2268 ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ 2269 : (max >= 0x200) ? HImode \ 2270 : QImode) 2271 2272 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2273 unsigned is probably best, but may break some code. */ 2274 #ifndef DEFAULT_SIGNED_CHAR 2275 #define DEFAULT_SIGNED_CHAR 0 2276 #endif 2277 2278 /* Max number of bytes we can move from memory to memory 2279 in one reasonably fast instruction. */ 2280 #define MOVE_MAX 4 2281 2282 #undef MOVE_RATIO 2283 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2284 2285 /* Define if operations between registers always perform the operation 2286 on the full register even if a narrower mode is specified. */ 2287 #define WORD_REGISTER_OPERATIONS 2288 2289 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2290 will either zero-extend or sign-extend. The value of this macro should 2291 be the code that says which one of the two operations is implicitly 2292 done, UNKNOWN if none. */ 2293 #define LOAD_EXTEND_OP(MODE) \ 2294 (TARGET_THUMB ? ZERO_EXTEND : \ 2295 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2296 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2297 2298 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2299 #define SLOW_BYTE_ACCESS 0 2300 2301 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2302 2303 /* Immediate shift counts are truncated by the output routines (or was it 2304 the assembler?). Shift counts in a register are truncated by ARM. Note 2305 that the native compiler puts too large (> 32) immediate shift counts 2306 into a register and shifts by the register, letting the ARM decide what 2307 to do instead of doing that itself. */ 2308 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2309 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2310 On the arm, Y in a register is used modulo 256 for the shift. Only for 2311 rotates is modulo 32 used. */ 2312 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2313 2314 /* All integers have the same format so truncation is easy. */ 2315 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2316 2317 /* Calling from registers is a massive pain. */ 2318 #define NO_FUNCTION_CSE 1 2319 2320 /* The machine modes of pointers and functions */ 2321 #define Pmode SImode 2322 #define FUNCTION_MODE Pmode 2323 2324 #define ARM_FRAME_RTX(X) \ 2325 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2326 || (X) == arg_pointer_rtx) 2327 2328 /* Moves to and from memory are quite expensive */ 2329 #define MEMORY_MOVE_COST(M, CLASS, IN) \ 2330 (TARGET_32BIT ? 10 : \ 2331 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2332 * (CLASS == LO_REGS ? 1 : 2))) 2333 2334 /* Try to generate sequences that don't involve branches, we can then use 2335 conditional instructions */ 2336 #define BRANCH_COST(speed_p, predictable_p) \ 2337 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) 2338 2339 /* Position Independent Code. */ 2341 /* We decide which register to use based on the compilation options and 2342 the assembler in use; this is more general than the APCS restriction of 2343 using sb (r9) all the time. */ 2344 extern unsigned arm_pic_register; 2345 2346 /* The register number of the register used to address a table of static 2347 data addresses in memory. */ 2348 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2349 2350 /* We can't directly access anything that contains a symbol, 2351 nor can we indirect via the constant pool. One exception is 2352 UNSPEC_TLS, which is always PIC. */ 2353 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2354 (!(symbol_mentioned_p (X) \ 2355 || label_mentioned_p (X) \ 2356 || (GET_CODE (X) == SYMBOL_REF \ 2357 && CONSTANT_POOL_ADDRESS_P (X) \ 2358 && (symbol_mentioned_p (get_pool_constant (X)) \ 2359 || label_mentioned_p (get_pool_constant (X))))) \ 2360 || tls_mentioned_p (X)) 2361 2362 /* We need to know when we are making a constant pool; this determines 2363 whether data needs to be in the GOT or can be referenced via a GOT 2364 offset. */ 2365 extern int making_const_table; 2366 2367 /* Handle pragmas for compatibility with Intel's compilers. */ 2369 /* Also abuse this to register additional C specific EABI attributes. */ 2370 #define REGISTER_TARGET_PRAGMAS() do { \ 2371 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2372 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2373 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2374 arm_lang_object_attributes_init(); \ 2375 } while (0) 2376 2377 /* Condition code information. */ 2378 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2379 return the mode to be used for the comparison. */ 2380 2381 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2382 2383 #define REVERSIBLE_CC_MODE(MODE) 1 2384 2385 #define REVERSE_CONDITION(CODE,MODE) \ 2386 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2387 ? reverse_condition_maybe_unordered (code) \ 2388 : reverse_condition (code)) 2389 2390 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2391 do \ 2392 { \ 2393 if (GET_CODE (OP1) == CONST_INT \ 2394 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2395 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2396 { \ 2397 rtx const_op = OP1; \ 2398 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ 2399 &const_op); \ 2400 OP1 = const_op; \ 2401 } \ 2402 } \ 2403 while (0) 2404 2405 /* The arm5 clz instruction returns 32. */ 2406 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2407 2408 #undef ASM_APP_OFF 2410 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2411 TARGET_THUMB2 ? "\t.thumb\n" : "") 2412 2413 /* Output a push or a pop instruction (only used when profiling). */ 2414 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2415 do \ 2416 { \ 2417 if (TARGET_ARM) \ 2418 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2419 STACK_POINTER_REGNUM, REGNO); \ 2420 else \ 2421 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2422 } while (0) 2423 2424 2425 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2426 do \ 2427 { \ 2428 if (TARGET_ARM) \ 2429 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2430 STACK_POINTER_REGNUM, REGNO); \ 2431 else \ 2432 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2433 } while (0) 2434 2435 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 2436 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 2437 2438 /* This is how to output a label which precedes a jumptable. Since 2439 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2440 #undef ASM_OUTPUT_CASE_LABEL 2441 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2442 do \ 2443 { \ 2444 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 2445 ASM_OUTPUT_ALIGN (FILE, 2); \ 2446 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2447 } \ 2448 while (0) 2449 2450 /* Make sure subsequent insns are aligned after a TBB. */ 2451 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 2452 do \ 2453 { \ 2454 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ 2455 ASM_OUTPUT_ALIGN (FILE, 1); \ 2456 } \ 2457 while (0) 2458 2459 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2460 do \ 2461 { \ 2462 if (TARGET_THUMB) \ 2463 { \ 2464 if (is_called_in_ARM_mode (DECL) \ 2465 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2466 && cfun->is_thunk)) \ 2467 fprintf (STREAM, "\t.code 32\n") ; \ 2468 else if (TARGET_THUMB1) \ 2469 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2470 else \ 2471 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2472 } \ 2473 if (TARGET_POKE_FUNCTION_NAME) \ 2474 arm_poke_function_name (STREAM, (const char *) NAME); \ 2475 } \ 2476 while (0) 2477 2478 /* For aliases of functions we use .thumb_set instead. */ 2479 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2480 do \ 2481 { \ 2482 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2483 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2484 \ 2485 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2486 { \ 2487 fprintf (FILE, "\t.thumb_set "); \ 2488 assemble_name (FILE, LABEL1); \ 2489 fprintf (FILE, ","); \ 2490 assemble_name (FILE, LABEL2); \ 2491 fprintf (FILE, "\n"); \ 2492 } \ 2493 else \ 2494 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2495 } \ 2496 while (0) 2497 2498 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2499 /* To support -falign-* switches we need to use .p2align so 2500 that alignment directives in code sections will be padded 2501 with no-op instructions, rather than zeroes. */ 2502 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2503 if ((LOG) != 0) \ 2504 { \ 2505 if ((MAX_SKIP) == 0) \ 2506 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2507 else \ 2508 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2509 (int) (LOG), (int) (MAX_SKIP)); \ 2510 } 2511 #endif 2512 2513 /* Add two bytes to the length of conditionally executed Thumb-2 2515 instructions for the IT instruction. */ 2516 #define ADJUST_INSN_LENGTH(insn, length) \ 2517 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2518 length += 2; 2519 2520 /* Only perform branch elimination (by making instructions conditional) if 2521 we're optimizing. For Thumb-2 check if any IT instructions need 2522 outputting. */ 2523 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2524 if (TARGET_ARM && optimize) \ 2525 arm_final_prescan_insn (INSN); \ 2526 else if (TARGET_THUMB2) \ 2527 thumb2_final_prescan_insn (INSN); \ 2528 else if (TARGET_THUMB1) \ 2529 thumb1_final_prescan_insn (INSN) 2530 2531 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2532 (CODE == '@' || CODE == '|' || CODE == '.' \ 2533 || CODE == '(' || CODE == ')' || CODE == '#' \ 2534 || (TARGET_32BIT && (CODE == '?')) \ 2535 || (TARGET_THUMB2 && (CODE == '!')) \ 2536 || (TARGET_THUMB && (CODE == '_'))) 2537 2538 /* Output an operand of an instruction. */ 2539 #define PRINT_OPERAND(STREAM, X, CODE) \ 2540 arm_print_operand (STREAM, X, CODE) 2541 2542 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2543 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2544 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2545 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2546 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2547 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2548 : 0)))) 2549 2550 /* Output the address of an operand. */ 2551 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2552 { \ 2553 int is_minus = GET_CODE (X) == MINUS; \ 2554 \ 2555 if (GET_CODE (X) == REG) \ 2556 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2557 else if (GET_CODE (X) == PLUS || is_minus) \ 2558 { \ 2559 rtx base = XEXP (X, 0); \ 2560 rtx index = XEXP (X, 1); \ 2561 HOST_WIDE_INT offset = 0; \ 2562 if (GET_CODE (base) != REG \ 2563 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \ 2564 { \ 2565 /* Ensure that BASE is a register. */ \ 2566 /* (one of them must be). */ \ 2567 /* Also ensure the SP is not used as in index register. */ \ 2568 rtx temp = base; \ 2569 base = index; \ 2570 index = temp; \ 2571 } \ 2572 switch (GET_CODE (index)) \ 2573 { \ 2574 case CONST_INT: \ 2575 offset = INTVAL (index); \ 2576 if (is_minus) \ 2577 offset = -offset; \ 2578 asm_fprintf (STREAM, "[%r, #%wd]", \ 2579 REGNO (base), offset); \ 2580 break; \ 2581 \ 2582 case REG: \ 2583 asm_fprintf (STREAM, "[%r, %s%r]", \ 2584 REGNO (base), is_minus ? "-" : "", \ 2585 REGNO (index)); \ 2586 break; \ 2587 \ 2588 case MULT: \ 2589 case ASHIFTRT: \ 2590 case LSHIFTRT: \ 2591 case ASHIFT: \ 2592 case ROTATERT: \ 2593 { \ 2594 asm_fprintf (STREAM, "[%r, %s%r", \ 2595 REGNO (base), is_minus ? "-" : "", \ 2596 REGNO (XEXP (index, 0))); \ 2597 arm_print_operand (STREAM, index, 'S'); \ 2598 fputs ("]", STREAM); \ 2599 break; \ 2600 } \ 2601 \ 2602 default: \ 2603 gcc_unreachable (); \ 2604 } \ 2605 } \ 2606 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2607 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2608 { \ 2609 extern enum machine_mode output_memory_reference_mode; \ 2610 \ 2611 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2612 \ 2613 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2614 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2615 REGNO (XEXP (X, 0)), \ 2616 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2617 GET_MODE_SIZE (output_memory_reference_mode)); \ 2618 else \ 2619 asm_fprintf (STREAM, "[%r], #%s%d", \ 2620 REGNO (XEXP (X, 0)), \ 2621 GET_CODE (X) == POST_DEC ? "-" : "", \ 2622 GET_MODE_SIZE (output_memory_reference_mode)); \ 2623 } \ 2624 else if (GET_CODE (X) == PRE_MODIFY) \ 2625 { \ 2626 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2627 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2628 asm_fprintf (STREAM, "#%wd]!", \ 2629 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2630 else \ 2631 asm_fprintf (STREAM, "%r]!", \ 2632 REGNO (XEXP (XEXP (X, 1), 1))); \ 2633 } \ 2634 else if (GET_CODE (X) == POST_MODIFY) \ 2635 { \ 2636 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2637 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2638 asm_fprintf (STREAM, "#%wd", \ 2639 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2640 else \ 2641 asm_fprintf (STREAM, "%r", \ 2642 REGNO (XEXP (XEXP (X, 1), 1))); \ 2643 } \ 2644 else output_addr_const (STREAM, X); \ 2645 } 2646 2647 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2648 { \ 2649 if (GET_CODE (X) == REG) \ 2650 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2651 else if (GET_CODE (X) == POST_INC) \ 2652 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2653 else if (GET_CODE (X) == PLUS) \ 2654 { \ 2655 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2656 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2657 asm_fprintf (STREAM, "[%r, #%wd]", \ 2658 REGNO (XEXP (X, 0)), \ 2659 INTVAL (XEXP (X, 1))); \ 2660 else \ 2661 asm_fprintf (STREAM, "[%r, %r]", \ 2662 REGNO (XEXP (X, 0)), \ 2663 REGNO (XEXP (X, 1))); \ 2664 } \ 2665 else \ 2666 output_addr_const (STREAM, X); \ 2667 } 2668 2669 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2670 if (TARGET_32BIT) \ 2671 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2672 else \ 2673 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2674 2675 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \ 2676 if (arm_output_addr_const_extra (file, x) == FALSE) \ 2677 goto fail 2678 2679 /* A C expression whose value is RTL representing the value of the return 2680 address for the frame COUNT steps up from the current frame. */ 2681 2682 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2683 arm_return_addr (COUNT, FRAME) 2684 2685 /* Mask of the bits in the PC that contain the real return address 2686 when running in 26-bit mode. */ 2687 #define RETURN_ADDR_MASK26 (0x03fffffc) 2688 2689 /* Pick up the return address upon entry to a procedure. Used for 2690 dwarf2 unwind information. This also enables the table driven 2691 mechanism. */ 2692 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2693 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2694 2695 /* Used to mask out junk bits from the return address, such as 2696 processor state, interrupt status, condition codes and the like. */ 2697 #define MASK_RETURN_ADDR \ 2698 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2699 in 26 bit mode, the condition codes must be masked out of the \ 2700 return address. This does not apply to ARM6 and later processors \ 2701 when running in 32 bit mode. */ \ 2702 ((arm_arch4 || TARGET_THUMB) \ 2703 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2704 : arm_gen_return_addr_mask ()) 2705 2706 2707 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have 2709 symbolic names defined here (which would require too much duplication). 2710 FIXME? */ 2711 enum arm_builtins 2712 { 2713 ARM_BUILTIN_GETWCX, 2714 ARM_BUILTIN_SETWCX, 2715 2716 ARM_BUILTIN_WZERO, 2717 2718 ARM_BUILTIN_WAVG2BR, 2719 ARM_BUILTIN_WAVG2HR, 2720 ARM_BUILTIN_WAVG2B, 2721 ARM_BUILTIN_WAVG2H, 2722 2723 ARM_BUILTIN_WACCB, 2724 ARM_BUILTIN_WACCH, 2725 ARM_BUILTIN_WACCW, 2726 2727 ARM_BUILTIN_WMACS, 2728 ARM_BUILTIN_WMACSZ, 2729 ARM_BUILTIN_WMACU, 2730 ARM_BUILTIN_WMACUZ, 2731 2732 ARM_BUILTIN_WSADB, 2733 ARM_BUILTIN_WSADBZ, 2734 ARM_BUILTIN_WSADH, 2735 ARM_BUILTIN_WSADHZ, 2736 2737 ARM_BUILTIN_WALIGN, 2738 2739 ARM_BUILTIN_TMIA, 2740 ARM_BUILTIN_TMIAPH, 2741 ARM_BUILTIN_TMIABB, 2742 ARM_BUILTIN_TMIABT, 2743 ARM_BUILTIN_TMIATB, 2744 ARM_BUILTIN_TMIATT, 2745 2746 ARM_BUILTIN_TMOVMSKB, 2747 ARM_BUILTIN_TMOVMSKH, 2748 ARM_BUILTIN_TMOVMSKW, 2749 2750 ARM_BUILTIN_TBCSTB, 2751 ARM_BUILTIN_TBCSTH, 2752 ARM_BUILTIN_TBCSTW, 2753 2754 ARM_BUILTIN_WMADDS, 2755 ARM_BUILTIN_WMADDU, 2756 2757 ARM_BUILTIN_WPACKHSS, 2758 ARM_BUILTIN_WPACKWSS, 2759 ARM_BUILTIN_WPACKDSS, 2760 ARM_BUILTIN_WPACKHUS, 2761 ARM_BUILTIN_WPACKWUS, 2762 ARM_BUILTIN_WPACKDUS, 2763 2764 ARM_BUILTIN_WADDB, 2765 ARM_BUILTIN_WADDH, 2766 ARM_BUILTIN_WADDW, 2767 ARM_BUILTIN_WADDSSB, 2768 ARM_BUILTIN_WADDSSH, 2769 ARM_BUILTIN_WADDSSW, 2770 ARM_BUILTIN_WADDUSB, 2771 ARM_BUILTIN_WADDUSH, 2772 ARM_BUILTIN_WADDUSW, 2773 ARM_BUILTIN_WSUBB, 2774 ARM_BUILTIN_WSUBH, 2775 ARM_BUILTIN_WSUBW, 2776 ARM_BUILTIN_WSUBSSB, 2777 ARM_BUILTIN_WSUBSSH, 2778 ARM_BUILTIN_WSUBSSW, 2779 ARM_BUILTIN_WSUBUSB, 2780 ARM_BUILTIN_WSUBUSH, 2781 ARM_BUILTIN_WSUBUSW, 2782 2783 ARM_BUILTIN_WAND, 2784 ARM_BUILTIN_WANDN, 2785 ARM_BUILTIN_WOR, 2786 ARM_BUILTIN_WXOR, 2787 2788 ARM_BUILTIN_WCMPEQB, 2789 ARM_BUILTIN_WCMPEQH, 2790 ARM_BUILTIN_WCMPEQW, 2791 ARM_BUILTIN_WCMPGTUB, 2792 ARM_BUILTIN_WCMPGTUH, 2793 ARM_BUILTIN_WCMPGTUW, 2794 ARM_BUILTIN_WCMPGTSB, 2795 ARM_BUILTIN_WCMPGTSH, 2796 ARM_BUILTIN_WCMPGTSW, 2797 2798 ARM_BUILTIN_TEXTRMSB, 2799 ARM_BUILTIN_TEXTRMSH, 2800 ARM_BUILTIN_TEXTRMSW, 2801 ARM_BUILTIN_TEXTRMUB, 2802 ARM_BUILTIN_TEXTRMUH, 2803 ARM_BUILTIN_TEXTRMUW, 2804 ARM_BUILTIN_TINSRB, 2805 ARM_BUILTIN_TINSRH, 2806 ARM_BUILTIN_TINSRW, 2807 2808 ARM_BUILTIN_WMAXSW, 2809 ARM_BUILTIN_WMAXSH, 2810 ARM_BUILTIN_WMAXSB, 2811 ARM_BUILTIN_WMAXUW, 2812 ARM_BUILTIN_WMAXUH, 2813 ARM_BUILTIN_WMAXUB, 2814 ARM_BUILTIN_WMINSW, 2815 ARM_BUILTIN_WMINSH, 2816 ARM_BUILTIN_WMINSB, 2817 ARM_BUILTIN_WMINUW, 2818 ARM_BUILTIN_WMINUH, 2819 ARM_BUILTIN_WMINUB, 2820 2821 ARM_BUILTIN_WMULUM, 2822 ARM_BUILTIN_WMULSM, 2823 ARM_BUILTIN_WMULUL, 2824 2825 ARM_BUILTIN_PSADBH, 2826 ARM_BUILTIN_WSHUFH, 2827 2828 ARM_BUILTIN_WSLLH, 2829 ARM_BUILTIN_WSLLW, 2830 ARM_BUILTIN_WSLLD, 2831 ARM_BUILTIN_WSRAH, 2832 ARM_BUILTIN_WSRAW, 2833 ARM_BUILTIN_WSRAD, 2834 ARM_BUILTIN_WSRLH, 2835 ARM_BUILTIN_WSRLW, 2836 ARM_BUILTIN_WSRLD, 2837 ARM_BUILTIN_WRORH, 2838 ARM_BUILTIN_WRORW, 2839 ARM_BUILTIN_WRORD, 2840 ARM_BUILTIN_WSLLHI, 2841 ARM_BUILTIN_WSLLWI, 2842 ARM_BUILTIN_WSLLDI, 2843 ARM_BUILTIN_WSRAHI, 2844 ARM_BUILTIN_WSRAWI, 2845 ARM_BUILTIN_WSRADI, 2846 ARM_BUILTIN_WSRLHI, 2847 ARM_BUILTIN_WSRLWI, 2848 ARM_BUILTIN_WSRLDI, 2849 ARM_BUILTIN_WRORHI, 2850 ARM_BUILTIN_WRORWI, 2851 ARM_BUILTIN_WRORDI, 2852 2853 ARM_BUILTIN_WUNPCKIHB, 2854 ARM_BUILTIN_WUNPCKIHH, 2855 ARM_BUILTIN_WUNPCKIHW, 2856 ARM_BUILTIN_WUNPCKILB, 2857 ARM_BUILTIN_WUNPCKILH, 2858 ARM_BUILTIN_WUNPCKILW, 2859 2860 ARM_BUILTIN_WUNPCKEHSB, 2861 ARM_BUILTIN_WUNPCKEHSH, 2862 ARM_BUILTIN_WUNPCKEHSW, 2863 ARM_BUILTIN_WUNPCKEHUB, 2864 ARM_BUILTIN_WUNPCKEHUH, 2865 ARM_BUILTIN_WUNPCKEHUW, 2866 ARM_BUILTIN_WUNPCKELSB, 2867 ARM_BUILTIN_WUNPCKELSH, 2868 ARM_BUILTIN_WUNPCKELSW, 2869 ARM_BUILTIN_WUNPCKELUB, 2870 ARM_BUILTIN_WUNPCKELUH, 2871 ARM_BUILTIN_WUNPCKELUW, 2872 2873 ARM_BUILTIN_THREAD_POINTER, 2874 2875 ARM_BUILTIN_NEON_BASE, 2876 2877 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ 2878 }; 2879 2880 /* Do not emit .note.GNU-stack by default. */ 2881 #ifndef NEED_INDICATE_EXEC_STACK 2882 #define NEED_INDICATE_EXEC_STACK 0 2883 #endif 2884 2885 #endif /* ! GCC_ARM_H */ 2886
