1 /* 2 * BusDrv.h 3 * 4 * Copyright(c) 1998 - 2009 Texas Instruments. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name Texas Instruments nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /** \file BusDrv.h 36 * \brief Bus-Driver module API definition 37 * 38 * \see SdioBusDrv.c, WspiBusDrv.c 39 */ 40 41 #ifndef __BUS_DRV_API_H__ 42 #define __BUS_DRV_API_H__ 43 44 45 #include "TxnDefs.h" 46 #include "queue.h" 47 48 49 /************************************************************************ 50 * Defines 51 ************************************************************************/ 52 53 #define WSPI_PAD_LEN_WRITE 4 54 #define WSPI_PAD_LEN_READ 8 55 #define MAX_XFER_BUFS 4 56 57 #define TXN_PARAM_STATUS_OK 0 58 #define TXN_PARAM_STATUS_ERROR 1 59 #define TXN_PARAM_STATUS_RECOVERY 2 60 61 #define TXN_DIRECTION_WRITE 0 62 #define TXN_DIRECTION_READ 1 63 64 #define TXN_HIGH_PRIORITY 0 65 #define TXN_LOW_PRIORITY 1 66 #define TXN_NUM_PRIORITYS 2 67 68 #define TXN_INC_ADDR 0 69 #define TXN_FIXED_ADDR 1 70 #define TXN_NON_SLEEP_ELP 1 71 #define TXN_SLEEP_ELP 0 72 73 #define NUM_OF_PARTITION 4 74 75 /************************************************************************ 76 * Macros 77 ************************************************************************/ 78 /* Get field from TTxnStruct->uTxnParams */ 79 #define TXN_PARAM_GET_PRIORITY(pTxn) ( (pTxn->uTxnParams & 0x00000003) >> 0 ) 80 #define TXN_PARAM_GET_FUNC_ID(pTxn) ( (pTxn->uTxnParams & 0x0000000C) >> 2 ) 81 #define TXN_PARAM_GET_DIRECTION(pTxn) ( (pTxn->uTxnParams & 0x00000010) >> 4 ) 82 #define TXN_PARAM_GET_FIXED_ADDR(pTxn) ( (pTxn->uTxnParams & 0x00000020) >> 5 ) 83 #define TXN_PARAM_GET_MORE(pTxn) ( (pTxn->uTxnParams & 0x00000040) >> 6 ) 84 #define TXN_PARAM_GET_SINGLE_STEP(pTxn) ( (pTxn->uTxnParams & 0x00000080) >> 7 ) 85 #define TXN_PARAM_GET_STATUS(pTxn) ( (pTxn->uTxnParams & 0x00000F00) >> 8 ) 86 87 /* Set field in TTxnStruct->uTxnParams */ 88 #define TXN_PARAM_SET_PRIORITY(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000003) | (uValue << 0 ) ) 89 #define TXN_PARAM_SET_FUNC_ID(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x0000000C) | (uValue << 2 ) ) 90 #define TXN_PARAM_SET_DIRECTION(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000010) | (uValue << 4 ) ) 91 #define TXN_PARAM_SET_FIXED_ADDR(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000020) | (uValue << 5 ) ) 92 #define TXN_PARAM_SET_MORE(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000040) | (uValue << 6 ) ) 93 #define TXN_PARAM_SET_SINGLE_STEP(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000080) | (uValue << 7 ) ) 94 #define TXN_PARAM_SET_STATUS(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000F00) | (uValue << 8 ) ) 95 96 #define TXN_PARAM_SET(pTxn, uPriority, uId, uDirection, uAddr) \ 97 TXN_PARAM_SET_PRIORITY(pTxn, uPriority); \ 98 TXN_PARAM_SET_FUNC_ID(pTxn, uId); \ 99 TXN_PARAM_SET_DIRECTION(pTxn, uDirection); \ 100 TXN_PARAM_SET_FIXED_ADDR(pTxn, uAddr); 101 102 #define BUILD_TTxnStruct(pTxn, uAddr, pBuf, uLen, fCB, hCB) \ 103 pTxn->aBuf[0] = (TI_UINT8*)(pBuf); \ 104 pTxn->aLen[0] = (TI_UINT16)(uLen); \ 105 pTxn->aLen[1] = 0; \ 106 pTxn->uHwAddr = uAddr; \ 107 pTxn->hCbHandle = (void*)hCB; \ 108 pTxn->fTxnDoneCb = (void*)fCB; 109 110 111 /************************************************************************ 112 * Types 113 ************************************************************************/ 114 /* The TxnDone CB called by the bus driver upon Async Txn completion */ 115 typedef void (*TBusDrvTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 116 117 /* The TxnDone CB called by the TxnQueue upon Async Txn completion */ 118 typedef void (*TTxnQueueDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 119 120 /* The TxnDone CB of the specific Txn originator (Xfer layer) called upon Async Txn completion */ 121 typedef void (*TTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); 122 123 /* The transactions structure */ 124 typedef struct 125 { 126 TQueNodeHdr tTxnQNode; /* Header for queueing */ 127 TI_UINT32 uTxnParams; /* Txn attributes (bit fields) - see macros above */ 128 TI_UINT32 uHwAddr; /* Physical (32 bits) HW Address */ 129 TTxnDoneCb fTxnDoneCb; /* CB called by TwIf upon Async Txn completion (may be NULL) */ 130 TI_HANDLE hCbHandle; /* The handle to use when calling fTxnDoneCb */ 131 TI_UINT16 aLen[MAX_XFER_BUFS]; /* Lengths of the following aBuf data buffers respectively. 132 Zero length marks last used buffer, or MAX_XFER_BUFS of all are used. */ 133 TI_UINT8* aBuf[MAX_XFER_BUFS]; /* Host data buffers to be written to or read from the device */ 134 TI_UINT8 aWspiPad[WSPI_PAD_LEN_READ]; /* Padding used by WSPI bus driver for its header or fixed-busy bytes */ 135 136 } TTxnStruct; 137 138 /* Parameters for all bus types configuration in ConnectBus process */ 139 140 typedef struct 141 { 142 TI_UINT32 uBlkSizeShift; 143 TI_UINT32 uBusDrvThreadPriority; 144 } TSdioCfg; 145 146 typedef struct 147 { 148 TI_UINT32 uDummy; 149 } TWspiCfg; 150 151 typedef struct 152 { 153 TI_UINT32 uBaudRate; 154 } TUartCfg; 155 156 typedef union 157 { 158 TSdioCfg tSdioCfg; 159 TWspiCfg tWspiCfg; 160 TUartCfg tUartCfg; 161 162 } TBusDrvCfg; 163 164 165 typedef struct 166 { 167 TI_UINT32 uMemAdrr; 168 TI_UINT32 uMemSize; 169 } TPartition; 170 171 /************************************************************************ 172 * Functions 173 ************************************************************************/ 174 TI_HANDLE busDrv_Create (TI_HANDLE hOs); 175 TI_STATUS busDrv_Destroy (TI_HANDLE hBusDrv); 176 void busDrv_Init (TI_HANDLE hBusDrv, TI_HANDLE hReport); 177 TI_STATUS busDrv_ConnectBus (TI_HANDLE hBusDrv, 178 TBusDrvCfg *pBusDrvCfg, 179 TBusDrvTxnDoneCb fCbFunc, 180 TI_HANDLE hCbArg, 181 TBusDrvTxnDoneCb fConnectCbFunc); 182 TI_STATUS busDrv_DisconnectBus (TI_HANDLE hBusDrv); 183 ETxnStatus busDrv_Transact (TI_HANDLE hBusDrv, TTxnStruct *pTxn); 184 185 #endif /*__BUS_DRV_API_H__*/ 186 187
