1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TargetMachine and LLVMTargetMachine classes. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETMACHINE_H 15 #define LLVM_TARGET_TARGETMACHINE_H 16 17 #include "llvm/MC/MCCodeGenInfo.h" 18 #include "llvm/ADT/StringRef.h" 19 #include <cassert> 20 #include <string> 21 22 namespace llvm { 23 24 class InstrItineraryData; 25 class JITCodeEmitter; 26 class MCAsmInfo; 27 class MCCodeGenInfo; 28 class MCContext; 29 class Pass; 30 class PassManager; 31 class PassManagerBase; 32 class Target; 33 class TargetData; 34 class TargetELFWriterInfo; 35 class TargetFrameLowering; 36 class TargetInstrInfo; 37 class TargetIntrinsicInfo; 38 class TargetJITInfo; 39 class TargetLowering; 40 class TargetRegisterInfo; 41 class TargetSelectionDAGInfo; 42 class TargetSubtargetInfo; 43 class formatted_raw_ostream; 44 class raw_ostream; 45 46 // Code model types. 47 namespace CodeModel { 48 enum Model { 49 Default, 50 Small, 51 Kernel, 52 Medium, 53 Large 54 }; 55 } 56 57 // Code generation optimization level. 58 namespace CodeGenOpt { 59 enum Level { 60 None, // -O0 61 Less, // -O1 62 Default, // -O2, -Os 63 Aggressive // -O3 64 }; 65 } 66 67 namespace Sched { 68 enum Preference { 69 None, // No preference 70 Latency, // Scheduling for shortest total latency. 71 RegPressure, // Scheduling for lowest register pressure. 72 Hybrid, // Scheduling for both latency and register pressure. 73 ILP // Scheduling for ILP in low register pressure mode. 74 }; 75 } 76 77 //===----------------------------------------------------------------------===// 78 /// 79 /// TargetMachine - Primary interface to the complete machine description for 80 /// the target machine. All target-specific information should be accessible 81 /// through this interface. 82 /// 83 class TargetMachine { 84 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT 85 void operator=(const TargetMachine &); // DO NOT IMPLEMENT 86 protected: // Can only create subclasses. 87 TargetMachine(const Target &T, StringRef TargetTriple, 88 StringRef CPU, StringRef FS); 89 90 /// getSubtargetImpl - virtual method implemented by subclasses that returns 91 /// a reference to that target's TargetSubtargetInfo-derived member variable. 92 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; } 93 94 /// TheTarget - The Target that this machine was created for. 95 const Target &TheTarget; 96 97 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target 98 /// feature strings the TargetMachine instance is created with. 99 std::string TargetTriple; 100 std::string TargetCPU; 101 std::string TargetFS; 102 103 /// CodeGenInfo - Low level target information such as relocation model. 104 /// 105 const MCCodeGenInfo *CodeGenInfo; 106 107 /// AsmInfo - Contains target specific asm information. 108 /// 109 const MCAsmInfo *AsmInfo; 110 111 unsigned MCRelaxAll : 1; 112 unsigned MCNoExecStack : 1; 113 unsigned MCSaveTempLabels : 1; 114 unsigned MCUseLoc : 1; 115 unsigned MCUseCFI : 1; 116 117 public: 118 virtual ~TargetMachine(); 119 120 const Target &getTarget() const { return TheTarget; } 121 122 const StringRef getTargetTriple() const { return TargetTriple; } 123 const StringRef getTargetCPU() const { return TargetCPU; } 124 const StringRef getTargetFeatureString() const { return TargetFS; } 125 126 // Interfaces to the major aspects of target machine information: 127 // -- Instruction opcode and operand information 128 // -- Pipelines and scheduling information 129 // -- Stack frame information 130 // -- Selection DAG lowering information 131 // 132 virtual const TargetInstrInfo *getInstrInfo() const { return 0; } 133 virtual const TargetFrameLowering *getFrameLowering() const { return 0; } 134 virtual const TargetLowering *getTargetLowering() const { return 0; } 135 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } 136 virtual const TargetData *getTargetData() const { return 0; } 137 138 /// getMCAsmInfo - Return target specific asm information. 139 /// 140 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 141 142 /// getSubtarget - This method returns a pointer to the specified type of 143 /// TargetSubtargetInfo. In debug builds, it verifies that the object being 144 /// returned is of the correct type. 145 template<typename STC> const STC &getSubtarget() const { 146 return *static_cast<const STC*>(getSubtargetImpl()); 147 } 148 149 /// getRegisterInfo - If register information is available, return it. If 150 /// not, return null. This is kept separate from RegInfo until RegInfo has 151 /// details of graph coloring register allocation removed from it. 152 /// 153 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; } 154 155 /// getIntrinsicInfo - If intrinsic information is available, return it. If 156 /// not, return null. 157 /// 158 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; } 159 160 /// getJITInfo - If this target supports a JIT, return information for it, 161 /// otherwise return null. 162 /// 163 virtual TargetJITInfo *getJITInfo() { return 0; } 164 165 /// getInstrItineraryData - Returns instruction itinerary data for the target 166 /// or specific subtarget. 167 /// 168 virtual const InstrItineraryData *getInstrItineraryData() const { 169 return 0; 170 } 171 172 /// getELFWriterInfo - If this target supports an ELF writer, return 173 /// information for it, otherwise return null. 174 /// 175 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; } 176 177 /// hasMCRelaxAll - Check whether all machine code instructions should be 178 /// relaxed. 179 bool hasMCRelaxAll() const { return MCRelaxAll; } 180 181 /// setMCRelaxAll - Set whether all machine code instructions should be 182 /// relaxed. 183 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; } 184 185 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved 186 /// (i.e., not treated as temporary). 187 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; } 188 189 /// setMCSaveTempLabels - Set whether temporary labels will be preserved 190 /// (i.e., not treated as temporary). 191 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; } 192 193 /// hasMCNoExecStack - Check whether an executable stack is not needed. 194 bool hasMCNoExecStack() const { return MCNoExecStack; } 195 196 /// setMCNoExecStack - Set whether an executabel stack is not needed. 197 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; } 198 199 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive. 200 bool hasMCUseLoc() const { return MCUseLoc; } 201 202 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive. 203 void setMCUseLoc(bool Value) { MCUseLoc = Value; } 204 205 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives. 206 bool hasMCUseCFI() const { return MCUseCFI; } 207 208 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives. 209 void setMCUseCFI(bool Value) { MCUseCFI = Value; } 210 211 /// getRelocationModel - Returns the code generation relocation model. The 212 /// choices are static, PIC, and dynamic-no-pic, and target default. 213 Reloc::Model getRelocationModel() const; 214 215 /// getCodeModel - Returns the code model. The choices are small, kernel, 216 /// medium, large, and target default. 217 static CodeModel::Model getCodeModel(); 218 219 /// setCodeModel - Sets the code model. 220 /// 221 static void setCodeModel(CodeModel::Model Model); 222 223 /// getAsmVerbosityDefault - Returns the default value of asm verbosity. 224 /// 225 static bool getAsmVerbosityDefault(); 226 227 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default 228 /// is false. 229 static void setAsmVerbosityDefault(bool); 230 231 /// getDataSections - Return true if data objects should be emitted into their 232 /// own section, corresponds to -fdata-sections. 233 static bool getDataSections(); 234 235 /// getFunctionSections - Return true if functions should be emitted into 236 /// their own section, corresponding to -ffunction-sections. 237 static bool getFunctionSections(); 238 239 /// setDataSections - Set if the data are emit into separate sections. 240 static void setDataSections(bool); 241 242 /// setFunctionSections - Set if the functions are emit into separate 243 /// sections. 244 static void setFunctionSections(bool); 245 246 /// CodeGenFileType - These enums are meant to be passed into 247 /// addPassesToEmitFile to indicate what type of file to emit, and returned by 248 /// it to indicate what type of file could actually be made. 249 enum CodeGenFileType { 250 CGFT_AssemblyFile, 251 CGFT_ObjectFile, 252 CGFT_Null // Do not emit any output. 253 }; 254 255 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 256 /// on this target. User flag overrides. 257 virtual bool getEnableTailMergeDefault() const { return true; } 258 259 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 260 /// specified file emitted. Typically this will involve several steps of code 261 /// generation. This method should return true if emission of this file type 262 /// is not supported, or false on success. 263 virtual bool addPassesToEmitFile(PassManagerBase &, 264 formatted_raw_ostream &, 265 CodeGenFileType, 266 CodeGenOpt::Level, 267 bool = true) { 268 return true; 269 } 270 271 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 272 /// get machine code emitted. This uses a JITCodeEmitter object to handle 273 /// actually outputting the machine code and resolving things like the address 274 /// of functions. This method returns true if machine code emission is 275 /// not supported. 276 /// 277 virtual bool addPassesToEmitMachineCode(PassManagerBase &, 278 JITCodeEmitter &, 279 CodeGenOpt::Level, 280 bool = true) { 281 return true; 282 } 283 284 /// addPassesToEmitMC - Add passes to the specified pass manager to get 285 /// machine code emitted with the MCJIT. This method returns true if machine 286 /// code is not supported. It fills the MCContext Ctx pointer which can be 287 /// used to build custom MCStreamer. 288 /// 289 virtual bool addPassesToEmitMC(PassManagerBase &, 290 MCContext *&, 291 raw_ostream &, 292 CodeGenOpt::Level, 293 bool = true) { 294 return true; 295 } 296 }; 297 298 /// LLVMTargetMachine - This class describes a target machine that is 299 /// implemented with the LLVM target-independent code generator. 300 /// 301 class LLVMTargetMachine : public TargetMachine { 302 protected: // Can only create subclasses. 303 LLVMTargetMachine(const Target &T, StringRef TargetTriple, 304 StringRef CPU, StringRef FS, Reloc::Model RM); 305 306 private: 307 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for 308 /// both emitting to assembly files or machine code output. 309 /// 310 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level, 311 bool DisableVerify, MCContext *&OutCtx); 312 313 virtual void setCodeModelForJIT(); 314 virtual void setCodeModelForStatic(); 315 316 public: 317 /// addPassesToEmitFile - Add passes to the specified pass manager to get the 318 /// specified file emitted. Typically this will involve several steps of code 319 /// generation. If OptLevel is None, the code generator should emit code as 320 /// fast as possible, though the generated code may be less efficient. 321 virtual bool addPassesToEmitFile(PassManagerBase &PM, 322 formatted_raw_ostream &Out, 323 CodeGenFileType FileType, 324 CodeGenOpt::Level, 325 bool DisableVerify = true); 326 327 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to 328 /// get machine code emitted. This uses a JITCodeEmitter object to handle 329 /// actually outputting the machine code and resolving things like the address 330 /// of functions. This method returns true if machine code emission is 331 /// not supported. 332 /// 333 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM, 334 JITCodeEmitter &MCE, 335 CodeGenOpt::Level, 336 bool DisableVerify = true); 337 338 /// addPassesToEmitMC - Add passes to the specified pass manager to get 339 /// machine code emitted with the MCJIT. This method returns true if machine 340 /// code is not supported. It fills the MCContext Ctx pointer which can be 341 /// used to build custom MCStreamer. 342 /// 343 virtual bool addPassesToEmitMC(PassManagerBase &PM, 344 MCContext *&Ctx, 345 raw_ostream &OS, 346 CodeGenOpt::Level OptLevel, 347 bool DisableVerify = true); 348 349 /// Target-Independent Code Generator Pass Configuration Options. 350 351 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM 352 /// passes (which are run just before instruction selector). 353 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) { 354 return true; 355 } 356 357 /// addInstSelector - This method should install an instruction selector pass, 358 /// which converts from LLVM code to machine instructions. 359 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) { 360 return true; 361 } 362 363 /// addPreRegAlloc - This method may be implemented by targets that want to 364 /// run passes immediately before register allocation. This should return 365 /// true if -print-machineinstrs should print after these passes. 366 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 367 return false; 368 } 369 370 /// addPostRegAlloc - This method may be implemented by targets that want 371 /// to run passes after register allocation but before prolog-epilog 372 /// insertion. This should return true if -print-machineinstrs should print 373 /// after these passes. 374 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) { 375 return false; 376 } 377 378 /// addPreSched2 - This method may be implemented by targets that want to 379 /// run passes after prolog-epilog insertion and before the second instruction 380 /// scheduling pass. This should return true if -print-machineinstrs should 381 /// print after these passes. 382 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) { 383 return false; 384 } 385 386 /// addPreEmitPass - This pass may be implemented by targets that want to run 387 /// passes immediately before machine code is emitted. This should return 388 /// true if -print-machineinstrs should print out the code after the passes. 389 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) { 390 return false; 391 } 392 393 394 /// addCodeEmitter - This pass should be overridden by the target to add a 395 /// code emitter, if supported. If this is not supported, 'true' should be 396 /// returned. 397 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level, 398 JITCodeEmitter &) { 399 return true; 400 } 401 402 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge 403 /// on this target. User flag overrides. 404 virtual bool getEnableTailMergeDefault() const { return true; } 405 }; 406 407 } // End llvm namespace 408 409 #endif 410
