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      1 //===- MBlazeInstrInfo.h - MBlaze Instruction Information -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the MBlaze implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef MBLAZEINSTRUCTIONINFO_H
     15 #define MBLAZEINSTRUCTIONINFO_H
     16 
     17 #include "MBlaze.h"
     18 #include "llvm/Support/ErrorHandling.h"
     19 #include "llvm/Target/TargetInstrInfo.h"
     20 #include "MBlazeRegisterInfo.h"
     21 
     22 #define GET_INSTRINFO_HEADER
     23 #include "MBlazeGenInstrInfo.inc"
     24 
     25 namespace llvm {
     26 
     27 namespace MBlaze {
     28 
     29   // MBlaze Branch Codes
     30   enum FPBranchCode {
     31     BRANCH_F,
     32     BRANCH_T,
     33     BRANCH_FL,
     34     BRANCH_TL,
     35     BRANCH_INVALID
     36   };
     37 
     38   // MBlaze Condition Codes
     39   enum CondCode {
     40     // To be used with float branch True
     41     FCOND_F,
     42     FCOND_UN,
     43     FCOND_EQ,
     44     FCOND_UEQ,
     45     FCOND_OLT,
     46     FCOND_ULT,
     47     FCOND_OLE,
     48     FCOND_ULE,
     49     FCOND_SF,
     50     FCOND_NGLE,
     51     FCOND_SEQ,
     52     FCOND_NGL,
     53     FCOND_LT,
     54     FCOND_NGE,
     55     FCOND_LE,
     56     FCOND_NGT,
     57 
     58     // To be used with float branch False
     59     // This conditions have the same mnemonic as the
     60     // above ones, but are used with a branch False;
     61     FCOND_T,
     62     FCOND_OR,
     63     FCOND_NEQ,
     64     FCOND_OGL,
     65     FCOND_UGE,
     66     FCOND_OGE,
     67     FCOND_UGT,
     68     FCOND_OGT,
     69     FCOND_ST,
     70     FCOND_GLE,
     71     FCOND_SNE,
     72     FCOND_GL,
     73     FCOND_NLT,
     74     FCOND_GE,
     75     FCOND_NLE,
     76     FCOND_GT,
     77 
     78     // Only integer conditions
     79     COND_EQ,
     80     COND_GT,
     81     COND_GE,
     82     COND_LT,
     83     COND_LE,
     84     COND_NE,
     85     COND_INVALID
     86   };
     87 
     88   // Turn condition code into conditional branch opcode.
     89   inline static unsigned GetCondBranchFromCond(CondCode CC) {
     90     switch (CC) {
     91     default: llvm_unreachable("Unknown condition code");
     92     case COND_EQ: return MBlaze::BEQID;
     93     case COND_NE: return MBlaze::BNEID;
     94     case COND_GT: return MBlaze::BGTID;
     95     case COND_GE: return MBlaze::BGEID;
     96     case COND_LT: return MBlaze::BLTID;
     97     case COND_LE: return MBlaze::BLEID;
     98     }
     99   }
    100 
    101   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
    102   /// e.g. turning COND_E to COND_NE.
    103   // CondCode GetOppositeBranchCondition(MBlaze::CondCode CC);
    104 
    105   /// MBlazeCCToString - Map each FP condition code to its string
    106   inline static const char *MBlazeFCCToString(MBlaze::CondCode CC) {
    107     switch (CC) {
    108     default: llvm_unreachable("Unknown condition code");
    109     case FCOND_F:
    110     case FCOND_T:   return "f";
    111     case FCOND_UN:
    112     case FCOND_OR:  return "un";
    113     case FCOND_EQ:
    114     case FCOND_NEQ: return "eq";
    115     case FCOND_UEQ:
    116     case FCOND_OGL: return "ueq";
    117     case FCOND_OLT:
    118     case FCOND_UGE: return "olt";
    119     case FCOND_ULT:
    120     case FCOND_OGE: return "ult";
    121     case FCOND_OLE:
    122     case FCOND_UGT: return "ole";
    123     case FCOND_ULE:
    124     case FCOND_OGT: return "ule";
    125     case FCOND_SF:
    126     case FCOND_ST:  return "sf";
    127     case FCOND_NGLE:
    128     case FCOND_GLE: return "ngle";
    129     case FCOND_SEQ:
    130     case FCOND_SNE: return "seq";
    131     case FCOND_NGL:
    132     case FCOND_GL:  return "ngl";
    133     case FCOND_LT:
    134     case FCOND_NLT: return "lt";
    135     case FCOND_NGE:
    136     case FCOND_GE:  return "ge";
    137     case FCOND_LE:
    138     case FCOND_NLE: return "nle";
    139     case FCOND_NGT:
    140     case FCOND_GT:  return "gt";
    141     }
    142   }
    143 
    144   inline static bool isUncondBranchOpcode(int Opc) {
    145     switch (Opc) {
    146     default: return false;
    147     case MBlaze::BRI:
    148     case MBlaze::BRAI:
    149     case MBlaze::BRID:
    150     case MBlaze::BRAID:
    151       return true;
    152     }
    153   }
    154 
    155   inline static bool isCondBranchOpcode(int Opc) {
    156     switch (Opc) {
    157     default: return false;
    158     case MBlaze::BEQI: case MBlaze::BEQID:
    159     case MBlaze::BNEI: case MBlaze::BNEID:
    160     case MBlaze::BGTI: case MBlaze::BGTID:
    161     case MBlaze::BGEI: case MBlaze::BGEID:
    162     case MBlaze::BLTI: case MBlaze::BLTID:
    163     case MBlaze::BLEI: case MBlaze::BLEID:
    164       return true;
    165     }
    166   }
    167 }
    168 
    169 /// MBlazeII - This namespace holds all of the target specific flags that
    170 /// instruction info tracks.
    171 ///
    172 namespace MBlazeII {
    173   enum {
    174     // PseudoFrm - This represents an instruction that is a pseudo instruction
    175     // or one that has not been implemented yet.  It is illegal to code generate
    176     // it, but tolerated for intermediate implementation stages.
    177     FPseudo = 0,
    178     FRRR,
    179     FRRI,
    180     FCRR,
    181     FCRI,
    182     FRCR,
    183     FRCI,
    184     FCCR,
    185     FCCI,
    186     FRRCI,
    187     FRRC,
    188     FRCX,
    189     FRCS,
    190     FCRCS,
    191     FCRCX,
    192     FCX,
    193     FCR,
    194     FRIR,
    195     FRRRR,
    196     FRI,
    197     FC,
    198     FormMask = 63
    199 
    200     //===------------------------------------------------------------------===//
    201     // MBlaze Specific MachineOperand flags.
    202     // MO_NO_FLAG,
    203 
    204     /// MO_GOT - Represents the offset into the global offset table at which
    205     /// the address the relocation entry symbol resides during execution.
    206     // MO_GOT,
    207 
    208     /// MO_GOT_CALL - Represents the offset into the global offset table at
    209     /// which the address of a call site relocation entry symbol resides
    210     /// during execution. This is different from the above since this flag
    211     /// can only be present in call instructions.
    212     // MO_GOT_CALL,
    213 
    214     /// MO_GPREL - Represents the offset from the current gp value to be used
    215     /// for the relocatable object file being produced.
    216     // MO_GPREL,
    217 
    218     /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
    219     /// address.
    220     // MO_ABS_HILO
    221 
    222   };
    223 }
    224 
    225 class MBlazeInstrInfo : public MBlazeGenInstrInfo {
    226   MBlazeTargetMachine &TM;
    227   const MBlazeRegisterInfo RI;
    228 public:
    229   explicit MBlazeInstrInfo(MBlazeTargetMachine &TM);
    230 
    231   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
    232   /// such, whenever a client has an instance of instruction info, it should
    233   /// always be able to get register info as well (through this method).
    234   ///
    235   virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; }
    236 
    237   /// isLoadFromStackSlot - If the specified machine instruction is a direct
    238   /// load from a stack slot, return the virtual or physical register number of
    239   /// the destination along with the FrameIndex of the loaded stack slot.  If
    240   /// not, return 0.  This predicate must return 0 if the instruction has
    241   /// any side effects other than loading from the stack slot.
    242   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
    243                                        int &FrameIndex) const;
    244 
    245   /// isStoreToStackSlot - If the specified machine instruction is a direct
    246   /// store to a stack slot, return the virtual or physical register number of
    247   /// the source reg along with the FrameIndex of the loaded stack slot.  If
    248   /// not, return 0.  This predicate must return 0 if the instruction has
    249   /// any side effects other than storing to the stack slot.
    250   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
    251                                       int &FrameIndex) const;
    252 
    253   /// Branch Analysis
    254   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
    255                              MachineBasicBlock *&FBB,
    256                              SmallVectorImpl<MachineOperand> &Cond,
    257                              bool AllowModify) const;
    258   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
    259                                 MachineBasicBlock *FBB,
    260                                 const SmallVectorImpl<MachineOperand> &Cond,
    261                                 DebugLoc DL) const;
    262   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
    263 
    264   virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
    265     const;
    266 
    267   virtual void copyPhysReg(MachineBasicBlock &MBB,
    268                            MachineBasicBlock::iterator I, DebugLoc DL,
    269                            unsigned DestReg, unsigned SrcReg,
    270                            bool KillSrc) const;
    271   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
    272                                    MachineBasicBlock::iterator MBBI,
    273                                    unsigned SrcReg, bool isKill, int FrameIndex,
    274                                    const TargetRegisterClass *RC,
    275                                    const TargetRegisterInfo *TRI) const;
    276 
    277   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
    278                                     MachineBasicBlock::iterator MBBI,
    279                                     unsigned DestReg, int FrameIndex,
    280                                     const TargetRegisterClass *RC,
    281                                     const TargetRegisterInfo *TRI) const;
    282 
    283   /// Insert nop instruction when hazard condition is found
    284   virtual void insertNoop(MachineBasicBlock &MBB,
    285                           MachineBasicBlock::iterator MI) const;
    286 
    287   /// getGlobalBaseReg - Return a virtual register initialized with the
    288   /// the global base register value. Output instructions required to
    289   /// initialize the register in the function entry block, if necessary.
    290   ///
    291   unsigned getGlobalBaseReg(MachineFunction *MF) const;
    292 };
    293 
    294 }
    295 
    296 #endif
    297