| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
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| ssearch.cpp | 674 struct Order
676 int32_t order; member in struct:Order
689 void add(int32_t order, int32_t low, int32_t high);
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
716 int32_t order, low, high; local
732 list = new Order[listMax];
738 order = ucol_next(elems, &status);
741 if (order != UCOL_NULLORDER)
788 const Order *order = get(index); local
799 const Order *order = get(index); local
810 const Order *order = get(index); local
875 const Order *order = list.get(i); local
893 const Order *order = list.get(i); local
991 int32_t order, low, high; local
1116 uint64_t order; local
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
43 // The remaining allocation order may depend on the hint.
44 ArrayRef<unsigned> Order =
47 if (Order.empty())
50 // Copy the allocation order with reserved registers removed.
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i])
[all...] |
| RegisterClassInfo.h | 31 OwningArrayPtr<unsigned> Order;
35 return makeArrayRef(Order.get(), NumRegs);
83 /// getOrder - Returns the preferred allocation order for RC. The order
111 /// Allocatable registers may show up in the allocation order of some virtual
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| CriticalAntiDepBreaker.cpp | 388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
389 for (unsigned i = 0; i != Order.size(); ++i) {
390 unsigned NewReg = Order[i];
525 // the anti-dependencies in an instruction in order to be effective.
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| RegAllocBasic.cpp | 485 ArrayRef<unsigned> Order =
487 for (ArrayRef<unsigned>::iterator I = Order.begin(), E = Order.end(); I != E;
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| RegAllocLinearScan.cpp | 148 /// handled_ - Intervals are added to the handled_ set in the order of their
613 // physical register or spill an interval (possibly this one) in order to
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
77 for (unsigned i = 0; i != Order.size(); ++i)
78 R.set(Order[i]);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
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| ScheduleDAGSDNodes.cpp | 169 /// outputs to ensure they are scheduled together and in order. This
209 // Sort them in increasing order.
231 // ensure they are scheduled in order of increasing addresses.
284 // Add all nodes in depth first order.
448 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
638 unsigned Order) {
643 // order number right after the N.
651 if (!Order || DVOrder == ++Order) {
662 // ProcessSourceNode - Process nodes with source order numbers. These are adde
[all...] |
| SelectionDAG.cpp | [all...] |
| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 184 // Sort by name to get a stable order.
253 // getSubRegs() orders by SubRegIndex. We want a topological order.
414 ArrayRef<Record*> Order = RC.getOrder();
418 AllocatableRegs.insert(Order.begin(), Order.end());
427 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
428 Record *Reg = Order[i];
641 OS << " static const ArrayRef<unsigned> Order[] = {\n"
647 << ");\n return Order[Select];\n}\n";
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| CodeGenRegisters.cpp | 72 // Here the order is important - earlier subregs take precedence.
78 // This creates a topological ordering, the exact order depends on the
79 // order getSubRegs is called on all registers.
275 // Default allocation order always contains all registers.
283 SetTheory::RecSet Order;
285 RegBank.getSets().evaluate(Alts->getElement(i), Order);
286 AltOrders[i].append(Order.begin(), Order.end());
288 while (!Order.empty()) {
289 CodeGenRegister *Reg = RegBank.getReg(Order.back())
[all...] |
| /external/llvm/lib/MC/ |
| MachObjectWriter.cpp | 367 // when we see the attribute, but that makes getting the order in the symbol
439 // The particular order that we collect the symbols and create the string
511 // External and undefined symbols are required to be in lexicographic order.
532 const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
533 for (int i = 0, n = Order.size(); i != n ; ++i) {
534 const MCSectionData *SD = Order[i];
732 // Write the section relocation entries, in reverse order to match 'as'
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 51 Order ///< Any other ordering dependency.
66 /// Order - Additional information about Order dependencies.
80 } Order;
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
110 case Order:
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial
[all...] |
| /external/mesa3d/src/mesa/main/ |
| mtypes.h | 993 /* Fields are in the order in which they're applied... */
[all...] |
