1 2 /*---------------------------------------------------------------*/ 3 /*--- begin host_ppc_defs.h ---*/ 4 /*---------------------------------------------------------------*/ 5 6 /* 7 This file is part of Valgrind, a dynamic binary instrumentation 8 framework. 9 10 Copyright (C) 2004-2010 OpenWorks LLP 11 info (at) open-works.net 12 13 This program is free software; you can redistribute it and/or 14 modify it under the terms of the GNU General Public License as 15 published by the Free Software Foundation; either version 2 of the 16 License, or (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, but 19 WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21 General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26 02110-1301, USA. 27 28 The GNU General Public License is contained in the file COPYING. 29 30 Neither the names of the U.S. Department of Energy nor the 31 University of California nor the names of its contributors may be 32 used to endorse or promote products derived from this software 33 without prior written permission. 34 */ 35 36 #ifndef __VEX_HOST_PPC_DEFS_H 37 #define __VEX_HOST_PPC_DEFS_H 38 39 /* Num registers used for function calls */ 40 #define PPC_N_REGPARMS 8 41 42 43 /* --------- Registers. --------- */ 44 45 /* The usual HReg abstraction. There are 32 real int regs, 46 32 real float regs, and 32 real vector regs. 47 */ 48 49 extern void ppHRegPPC ( HReg ); 50 51 extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg 52 extern HReg hregPPC_GPR1 ( Bool mode64 ); // Stack Frame Pointer 53 extern HReg hregPPC_GPR2 ( Bool mode64 ); // not used: TOC pointer 54 extern HReg hregPPC_GPR3 ( Bool mode64 ); 55 extern HReg hregPPC_GPR4 ( Bool mode64 ); 56 extern HReg hregPPC_GPR5 ( Bool mode64 ); 57 extern HReg hregPPC_GPR6 ( Bool mode64 ); 58 extern HReg hregPPC_GPR7 ( Bool mode64 ); 59 extern HReg hregPPC_GPR8 ( Bool mode64 ); 60 extern HReg hregPPC_GPR9 ( Bool mode64 ); 61 extern HReg hregPPC_GPR10 ( Bool mode64 ); 62 extern HReg hregPPC_GPR11 ( Bool mode64 ); 63 extern HReg hregPPC_GPR12 ( Bool mode64 ); 64 extern HReg hregPPC_GPR13 ( Bool mode64 ); 65 extern HReg hregPPC_GPR14 ( Bool mode64 ); 66 extern HReg hregPPC_GPR15 ( Bool mode64 ); 67 extern HReg hregPPC_GPR16 ( Bool mode64 ); 68 extern HReg hregPPC_GPR17 ( Bool mode64 ); 69 extern HReg hregPPC_GPR18 ( Bool mode64 ); 70 extern HReg hregPPC_GPR19 ( Bool mode64 ); 71 extern HReg hregPPC_GPR20 ( Bool mode64 ); 72 extern HReg hregPPC_GPR21 ( Bool mode64 ); 73 extern HReg hregPPC_GPR22 ( Bool mode64 ); 74 extern HReg hregPPC_GPR23 ( Bool mode64 ); 75 extern HReg hregPPC_GPR24 ( Bool mode64 ); 76 extern HReg hregPPC_GPR25 ( Bool mode64 ); 77 extern HReg hregPPC_GPR26 ( Bool mode64 ); 78 extern HReg hregPPC_GPR27 ( Bool mode64 ); 79 extern HReg hregPPC_GPR28 ( Bool mode64 ); 80 extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher 81 extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp 82 extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved) 83 84 extern HReg hregPPC_FPR0 ( void ); 85 extern HReg hregPPC_FPR1 ( void ); 86 extern HReg hregPPC_FPR2 ( void ); 87 extern HReg hregPPC_FPR3 ( void ); 88 extern HReg hregPPC_FPR4 ( void ); 89 extern HReg hregPPC_FPR5 ( void ); 90 extern HReg hregPPC_FPR6 ( void ); 91 extern HReg hregPPC_FPR7 ( void ); 92 extern HReg hregPPC_FPR8 ( void ); 93 extern HReg hregPPC_FPR9 ( void ); 94 extern HReg hregPPC_FPR10 ( void ); 95 extern HReg hregPPC_FPR11 ( void ); 96 extern HReg hregPPC_FPR12 ( void ); 97 extern HReg hregPPC_FPR13 ( void ); 98 extern HReg hregPPC_FPR14 ( void ); 99 extern HReg hregPPC_FPR15 ( void ); 100 extern HReg hregPPC_FPR16 ( void ); 101 extern HReg hregPPC_FPR17 ( void ); 102 extern HReg hregPPC_FPR18 ( void ); 103 extern HReg hregPPC_FPR19 ( void ); 104 extern HReg hregPPC_FPR20 ( void ); 105 extern HReg hregPPC_FPR21 ( void ); 106 extern HReg hregPPC_FPR22 ( void ); 107 extern HReg hregPPC_FPR23 ( void ); 108 extern HReg hregPPC_FPR24 ( void ); 109 extern HReg hregPPC_FPR25 ( void ); 110 extern HReg hregPPC_FPR26 ( void ); 111 extern HReg hregPPC_FPR27 ( void ); 112 extern HReg hregPPC_FPR28 ( void ); 113 extern HReg hregPPC_FPR29 ( void ); 114 extern HReg hregPPC_FPR30 ( void ); 115 extern HReg hregPPC_FPR31 ( void ); 116 117 extern HReg hregPPC_VR0 ( void ); 118 extern HReg hregPPC_VR1 ( void ); 119 extern HReg hregPPC_VR2 ( void ); 120 extern HReg hregPPC_VR3 ( void ); 121 extern HReg hregPPC_VR4 ( void ); 122 extern HReg hregPPC_VR5 ( void ); 123 extern HReg hregPPC_VR6 ( void ); 124 extern HReg hregPPC_VR7 ( void ); 125 extern HReg hregPPC_VR8 ( void ); 126 extern HReg hregPPC_VR9 ( void ); 127 extern HReg hregPPC_VR10 ( void ); 128 extern HReg hregPPC_VR11 ( void ); 129 extern HReg hregPPC_VR12 ( void ); 130 extern HReg hregPPC_VR13 ( void ); 131 extern HReg hregPPC_VR14 ( void ); 132 extern HReg hregPPC_VR15 ( void ); 133 extern HReg hregPPC_VR16 ( void ); 134 extern HReg hregPPC_VR17 ( void ); 135 extern HReg hregPPC_VR18 ( void ); 136 extern HReg hregPPC_VR19 ( void ); 137 extern HReg hregPPC_VR20 ( void ); 138 extern HReg hregPPC_VR21 ( void ); 139 extern HReg hregPPC_VR22 ( void ); 140 extern HReg hregPPC_VR23 ( void ); 141 extern HReg hregPPC_VR24 ( void ); 142 extern HReg hregPPC_VR25 ( void ); 143 extern HReg hregPPC_VR26 ( void ); 144 extern HReg hregPPC_VR27 ( void ); 145 extern HReg hregPPC_VR28 ( void ); 146 extern HReg hregPPC_VR29 ( void ); 147 extern HReg hregPPC_VR30 ( void ); 148 extern HReg hregPPC_VR31 ( void ); 149 150 #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) 151 #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) 152 153 154 155 /* --------- Condition codes --------- */ 156 157 /* This gives names from bitfields in CR; hence it names BI numbers */ 158 /* Using IBM/hardware indexing convention */ 159 typedef 160 enum { 161 // CR7, which we use for integer compares 162 Pcf_7LT = 28, /* neg | lt */ 163 Pcf_7GT = 29, /* pos | gt */ 164 Pcf_7EQ = 30, /* zero | equal */ 165 Pcf_7SO = 31 /* summary overflow */ 166 } 167 PPCCondFlag; 168 169 typedef 170 enum { /* Maps bc bitfield BO */ 171 Pct_FALSE = 0x4, 172 Pct_TRUE = 0xC, 173 Pct_ALWAYS = 0x14 174 } 175 PPCCondTest; 176 177 typedef 178 struct { 179 PPCCondFlag flag; 180 PPCCondTest test; 181 } 182 PPCCondCode; 183 184 extern HChar* showPPCCondCode ( PPCCondCode ); 185 186 /* constructor */ 187 extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); 188 189 /* false->true, true->false */ 190 extern PPCCondTest invertCondTest ( PPCCondTest ); 191 192 193 194 195 /* --------- Memory address expressions (amodes). --------- */ 196 197 typedef 198 enum { 199 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ 200 Pam_RR=2 /* Reg1 + Reg2 */ 201 } 202 PPCAModeTag; 203 204 typedef 205 struct { 206 PPCAModeTag tag; 207 union { 208 struct { 209 HReg base; 210 Int index; 211 } IR; 212 struct { 213 HReg base; 214 HReg index; 215 } RR; 216 } Pam; 217 } 218 PPCAMode; 219 220 extern PPCAMode* PPCAMode_IR ( Int, HReg ); 221 extern PPCAMode* PPCAMode_RR ( HReg, HReg ); 222 223 extern PPCAMode* dopyPPCAMode ( PPCAMode* ); 224 225 extern void ppPPCAMode ( PPCAMode* ); 226 227 228 /* --------- Operand, which can be a reg or a u16/s16. --------- */ 229 /* ("RH" == "Register or Halfword immediate") */ 230 typedef 231 enum { 232 Prh_Imm=3, 233 Prh_Reg=4 234 } 235 PPCRHTag; 236 237 typedef 238 struct { 239 PPCRHTag tag; 240 union { 241 struct { 242 Bool syned; 243 UShort imm16; 244 } Imm; 245 struct { 246 HReg reg; 247 } Reg; 248 } 249 Prh; 250 } 251 PPCRH; 252 253 extern PPCRH* PPCRH_Imm ( Bool, UShort ); 254 extern PPCRH* PPCRH_Reg ( HReg ); 255 256 extern void ppPPCRH ( PPCRH* ); 257 258 259 /* --------- Operand, which can be a reg or a u32/64. --------- */ 260 261 typedef 262 enum { 263 Pri_Imm=5, 264 Pri_Reg=6 265 } 266 PPCRITag; 267 268 typedef 269 struct { 270 PPCRITag tag; 271 union { 272 ULong Imm; 273 HReg Reg; 274 } 275 Pri; 276 } 277 PPCRI; 278 279 extern PPCRI* PPCRI_Imm ( ULong ); 280 extern PPCRI* PPCRI_Reg( HReg ); 281 282 extern void ppPPCRI ( PPCRI* ); 283 284 285 /* --------- Operand, which can be a vector reg or a s6. --------- */ 286 /* ("VI" == "Vector Register or Immediate") */ 287 typedef 288 enum { 289 Pvi_Imm=7, 290 Pvi_Reg=8 291 } 292 PPCVI5sTag; 293 294 typedef 295 struct { 296 PPCVI5sTag tag; 297 union { 298 Char Imm5s; 299 HReg Reg; 300 } 301 Pvi; 302 } 303 PPCVI5s; 304 305 extern PPCVI5s* PPCVI5s_Imm ( Char ); 306 extern PPCVI5s* PPCVI5s_Reg ( HReg ); 307 308 extern void ppPPCVI5s ( PPCVI5s* ); 309 310 311 /* --------- Instructions. --------- */ 312 313 /* --------- */ 314 typedef 315 enum { 316 Pun_NEG, 317 Pun_NOT, 318 Pun_CLZ32, 319 Pun_CLZ64, 320 Pun_EXTSW 321 } 322 PPCUnaryOp; 323 324 extern HChar* showPPCUnaryOp ( PPCUnaryOp ); 325 326 327 /* --------- */ 328 typedef 329 enum { 330 Palu_INVALID, 331 Palu_ADD, Palu_SUB, 332 Palu_AND, Palu_OR, Palu_XOR, 333 } 334 PPCAluOp; 335 336 extern 337 HChar* showPPCAluOp ( PPCAluOp, 338 Bool /* is the 2nd operand an immediate? */); 339 340 341 /* --------- */ 342 typedef 343 enum { 344 Pshft_INVALID, 345 Pshft_SHL, Pshft_SHR, Pshft_SAR, 346 } 347 PPCShftOp; 348 349 extern 350 HChar* showPPCShftOp ( PPCShftOp, 351 Bool /* is the 2nd operand an immediate? */, 352 Bool /* is this a 32bit or 64bit op? */ ); 353 354 355 /* --------- */ 356 typedef 357 enum { 358 Pfp_INVALID, 359 360 /* Ternary */ 361 Pfp_MADDD, Pfp_MSUBD, 362 Pfp_MADDS, Pfp_MSUBS, 363 364 /* Binary */ 365 Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, 366 Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, 367 368 /* Unary */ 369 Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE, 370 Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ 371 } 372 PPCFpOp; 373 374 extern HChar* showPPCFpOp ( PPCFpOp ); 375 376 377 /* --------- */ 378 typedef 379 enum { 380 Pav_INVALID, 381 382 /* Integer Unary */ 383 Pav_MOV, /* Mov */ 384 Pav_NOT, /* Bitwise */ 385 Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ 386 Pav_UNPCKL8S, Pav_UNPCKL16S, 387 Pav_UNPCKHPIX, Pav_UNPCKLPIX, 388 389 /* Integer Binary */ 390 Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ 391 Pav_ADDU, Pav_QADDU, Pav_QADDS, 392 Pav_SUBU, Pav_QSUBU, Pav_QSUBS, 393 Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, 394 Pav_AVGU, Pav_AVGS, 395 Pav_MAXU, Pav_MAXS, 396 Pav_MINU, Pav_MINS, 397 398 /* Compare (always affects CR field 6) */ 399 Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, 400 401 /* Shift */ 402 Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, 403 404 /* Pack */ 405 Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, 406 Pav_PACKPXL, 407 408 /* Merge */ 409 Pav_MRGHI, Pav_MRGLO, 410 } 411 PPCAvOp; 412 413 extern HChar* showPPCAvOp ( PPCAvOp ); 414 415 416 /* --------- */ 417 typedef 418 enum { 419 Pavfp_INVALID, 420 421 /* Floating point binary */ 422 Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, 423 Pavfp_MAXF, Pavfp_MINF, 424 Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, 425 426 /* Floating point unary */ 427 Pavfp_RCPF, Pavfp_RSQRTF, 428 Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, 429 Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, 430 } 431 PPCAvFpOp; 432 433 extern HChar* showPPCAvFpOp ( PPCAvFpOp ); 434 435 436 /* --------- */ 437 typedef 438 enum { 439 Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ 440 Pin_Alu, /* word add/sub/and/or/xor */ 441 Pin_Shft, /* word shl/shr/sar */ 442 Pin_AddSubC, /* add/sub with read/write carry */ 443 Pin_Cmp, /* word compare */ 444 Pin_Unary, /* not, neg, clz */ 445 Pin_MulL, /* widening multiply */ 446 Pin_Div, /* div */ 447 Pin_Call, /* call to address in register */ 448 Pin_Goto, /* conditional/unconditional jmp to dst */ 449 Pin_CMov, /* conditional move */ 450 Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ 451 Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */ 452 Pin_Store, /* store a 8|16|32|64 bit value to mem */ 453 Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */ 454 Pin_Set, /* convert condition code to value 0 or 1 */ 455 Pin_MfCR, /* move from condition register to GPR */ 456 Pin_MFence, /* mem fence */ 457 458 Pin_FpUnary, /* FP unary op */ 459 Pin_FpBinary, /* FP binary op */ 460 Pin_FpMulAcc, /* FP multipy-accumulate style op */ 461 Pin_FpLdSt, /* FP load/store */ 462 Pin_FpSTFIW, /* stfiwx */ 463 Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ 464 Pin_FpCftI, /* fcfid/fctid/fctiw */ 465 Pin_FpCMov, /* FP floating point conditional move */ 466 Pin_FpLdFPSCR, /* mtfsf */ 467 Pin_FpCmp, /* FP compare, generating value into int reg */ 468 469 Pin_RdWrLR, /* Read/Write Link Register */ 470 471 Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ 472 Pin_AvUnary, /* AV unary general reg=>reg */ 473 474 Pin_AvBinary, /* AV binary general reg,reg=>reg */ 475 Pin_AvBin8x16, /* AV binary, 8x4 */ 476 Pin_AvBin16x8, /* AV binary, 16x4 */ 477 Pin_AvBin32x4, /* AV binary, 32x4 */ 478 479 Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ 480 Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ 481 482 Pin_AvPerm, /* AV permute (shuffle) */ 483 Pin_AvSel, /* AV select */ 484 Pin_AvShlDbl, /* AV shift-left double by imm */ 485 Pin_AvSplat, /* One elem repeated throughout dst */ 486 Pin_AvLdVSCR, /* mtvscr */ 487 Pin_AvCMov /* AV conditional move */ 488 } 489 PPCInstrTag; 490 491 /* Destinations are on the LEFT (first operand) */ 492 493 typedef 494 struct { 495 PPCInstrTag tag; 496 union { 497 /* Get a 32/64-bit literal into a register. 498 May turn into a number of real insns. */ 499 struct { 500 HReg dst; 501 ULong imm64; 502 } LI; 503 /* Integer add/sub/and/or/xor. Limitations: 504 - For add, the immediate, if it exists, is a signed 16. 505 - For sub, the immediate, if it exists, is a signed 16 506 which may not be -32768, since no such instruction 507 exists, and so we have to emit addi with +32768, but 508 that is not possible. 509 - For and/or/xor, the immediate, if it exists, 510 is an unsigned 16. 511 */ 512 struct { 513 PPCAluOp op; 514 HReg dst; 515 HReg srcL; 516 PPCRH* srcR; 517 } Alu; 518 /* Integer shl/shr/sar. 519 Limitations: the immediate, if it exists, 520 is a signed 5-bit value between 1 and 31 inclusive. 521 */ 522 struct { 523 PPCShftOp op; 524 Bool sz32; /* mode64 has both 32 and 64bit shft */ 525 HReg dst; 526 HReg srcL; 527 PPCRH* srcR; 528 } Shft; 529 /* */ 530 struct { 531 Bool isAdd; /* else sub */ 532 Bool setC; /* else read carry */ 533 HReg dst; 534 HReg srcL; 535 HReg srcR; 536 } AddSubC; 537 /* If signed, the immediate, if it exists, is a signed 16, 538 else it is an unsigned 16. */ 539 struct { 540 Bool syned; 541 Bool sz32; /* mode64 has both 32 and 64bit cmp */ 542 UInt crfD; 543 HReg srcL; 544 PPCRH* srcR; 545 } Cmp; 546 /* Not, Neg, Clz32/64, Extsw */ 547 struct { 548 PPCUnaryOp op; 549 HReg dst; 550 HReg src; 551 } Unary; 552 struct { 553 Bool syned; /* meaningless if hi32==False */ 554 Bool hi; /* False=>low, True=>high */ 555 Bool sz32; /* mode64 has both 32 & 64bit mull */ 556 HReg dst; 557 HReg srcL; 558 HReg srcR; 559 } MulL; 560 /* ppc32 div/divu instruction. */ 561 struct { 562 Bool syned; 563 Bool sz32; /* mode64 has both 32 & 64bit div */ 564 HReg dst; 565 HReg srcL; 566 HReg srcR; 567 } Div; 568 /* Pseudo-insn. Call target (an absolute address), on given 569 condition (which could be Pct_ALWAYS). argiregs indicates 570 which of r3 .. r10 carries argument values for this call, 571 using a bit mask (1<<N is set if rN holds an arg, for N in 572 3 .. 10 inclusive). */ 573 struct { 574 PPCCondCode cond; 575 Addr64 target; 576 UInt argiregs; 577 } Call; 578 /* Pseudo-insn. Goto dst, on given condition (which could be 579 Pct_ALWAYS). */ 580 struct { 581 IRJumpKind jk; 582 PPCCondCode cond; 583 PPCRI* dst; 584 } Goto; 585 /* Mov src to dst on the given condition, which may not 586 be the bogus Pct_ALWAYS. */ 587 struct { 588 PPCCondCode cond; 589 HReg dst; 590 PPCRI* src; 591 } CMov; 592 /* Zero extending loads. Dst size is host word size */ 593 struct { 594 UChar sz; /* 1|2|4|8 */ 595 HReg dst; 596 PPCAMode* src; 597 } Load; 598 /* Load-and-reserve (lwarx, ldarx) */ 599 struct { 600 UChar sz; /* 4|8 */ 601 HReg dst; 602 HReg src; 603 } LoadL; 604 /* 64/32/16/8 bit stores */ 605 struct { 606 UChar sz; /* 1|2|4|8 */ 607 PPCAMode* dst; 608 HReg src; 609 } Store; 610 /* Store-conditional (stwcx., stdcx.) */ 611 struct { 612 UChar sz; /* 4|8 */ 613 HReg dst; 614 HReg src; 615 } StoreC; 616 /* Convert a ppc condition code to value 0 or 1. */ 617 struct { 618 PPCCondCode cond; 619 HReg dst; 620 } Set; 621 /* Move the entire CR to a GPR */ 622 struct { 623 HReg dst; 624 } MfCR; 625 /* Mem fence. In short, an insn which flushes all preceding 626 loads and stores as much as possible before continuing. 627 On PPC we emit a "sync". */ 628 struct { 629 } MFence; 630 631 /* PPC Floating point */ 632 struct { 633 PPCFpOp op; 634 HReg dst; 635 HReg src; 636 } FpUnary; 637 struct { 638 PPCFpOp op; 639 HReg dst; 640 HReg srcL; 641 HReg srcR; 642 } FpBinary; 643 struct { 644 PPCFpOp op; 645 HReg dst; 646 HReg srcML; 647 HReg srcMR; 648 HReg srcAcc; 649 } FpMulAcc; 650 struct { 651 Bool isLoad; 652 UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ 653 HReg reg; 654 PPCAMode* addr; 655 } FpLdSt; 656 struct { 657 HReg addr; /* int reg */ 658 HReg data; /* float reg */ 659 } FpSTFIW; 660 /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ 661 struct { 662 HReg src; 663 HReg dst; 664 } FpRSP; 665 /* fcfid/fctid/fctiw. Note there's no fcfiw so fromI==True 666 && int32==True is not allowed. */ 667 struct { 668 Bool fromI; /* False==F->I, True==I->F */ 669 Bool int32; /* True== I is 32, False==I is 64 */ 670 HReg src; 671 HReg dst; 672 } FpCftI; 673 /* FP mov src to dst on the given condition. */ 674 struct { 675 PPCCondCode cond; 676 HReg dst; 677 HReg src; 678 } FpCMov; 679 /* Load FP Status & Control Register */ 680 struct { 681 HReg src; 682 } FpLdFPSCR; 683 /* Do a compare, generating result into an int register. */ 684 struct { 685 UChar crfD; 686 HReg dst; 687 HReg srcL; 688 HReg srcR; 689 } FpCmp; 690 691 /* Read/Write Link Register */ 692 struct { 693 Bool wrLR; 694 HReg gpr; 695 } RdWrLR; 696 697 /* Simplistic AltiVec */ 698 struct { 699 Bool isLoad; 700 UChar sz; /* 8|16|32|128 */ 701 HReg reg; 702 PPCAMode* addr; 703 } AvLdSt; 704 struct { 705 PPCAvOp op; 706 HReg dst; 707 HReg src; 708 } AvUnary; 709 struct { 710 PPCAvOp op; 711 HReg dst; 712 HReg srcL; 713 HReg srcR; 714 } AvBinary; 715 struct { 716 PPCAvOp op; 717 HReg dst; 718 HReg srcL; 719 HReg srcR; 720 } AvBin8x16; 721 struct { 722 PPCAvOp op; 723 HReg dst; 724 HReg srcL; 725 HReg srcR; 726 } AvBin16x8; 727 struct { 728 PPCAvOp op; 729 HReg dst; 730 HReg srcL; 731 HReg srcR; 732 } AvBin32x4; 733 struct { 734 PPCAvFpOp op; 735 HReg dst; 736 HReg srcL; 737 HReg srcR; 738 } AvBin32Fx4; 739 struct { 740 PPCAvFpOp op; 741 HReg dst; 742 HReg src; 743 } AvUn32Fx4; 744 /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ 745 struct { 746 HReg dst; 747 HReg srcL; 748 HReg srcR; 749 HReg ctl; 750 } AvPerm; 751 struct { 752 HReg dst; 753 HReg srcL; 754 HReg srcR; 755 HReg ctl; 756 } AvSel; 757 struct { 758 UChar shift; 759 HReg dst; 760 HReg srcL; 761 HReg srcR; 762 } AvShlDbl; 763 struct { 764 UChar sz; /* 8,16,32 */ 765 HReg dst; 766 PPCVI5s* src; 767 } AvSplat; 768 /* Mov src to dst on the given condition, which may not 769 be the bogus Xcc_ALWAYS. */ 770 struct { 771 PPCCondCode cond; 772 HReg dst; 773 HReg src; 774 } AvCMov; 775 /* Load AltiVec Status & Control Register */ 776 struct { 777 HReg src; 778 } AvLdVSCR; 779 } Pin; 780 } 781 PPCInstr; 782 783 784 extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); 785 extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); 786 extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); 787 extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); 788 extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); 789 extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); 790 extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); 791 extern PPCInstr* PPCInstr_Div ( Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); 792 extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt ); 793 extern PPCInstr* PPCInstr_Goto ( IRJumpKind, PPCCondCode cond, PPCRI* dst ); 794 extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); 795 extern PPCInstr* PPCInstr_Load ( UChar sz, 796 HReg dst, PPCAMode* src, Bool mode64 ); 797 extern PPCInstr* PPCInstr_LoadL ( UChar sz, 798 HReg dst, HReg src, Bool mode64 ); 799 extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, 800 HReg src, Bool mode64 ); 801 extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, 802 Bool mode64 ); 803 extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); 804 extern PPCInstr* PPCInstr_MfCR ( HReg dst ); 805 extern PPCInstr* PPCInstr_MFence ( void ); 806 807 extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); 808 extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); 809 extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, 810 HReg srcMR, HReg srcAcc ); 811 extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); 812 extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); 813 extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); 814 extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, 815 HReg dst, HReg src ); 816 extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); 817 extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src ); 818 extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); 819 820 extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); 821 822 extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); 823 extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); 824 extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 825 extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 826 extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 827 extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 828 extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 829 extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvOp op, HReg dst, HReg src ); 830 extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); 831 extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); 832 extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); 833 extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); 834 extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); 835 extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); 836 837 extern void ppPPCInstr ( PPCInstr*, Bool mode64 ); 838 839 /* Some functions that insulate the register allocator from details 840 of the underlying instruction set. */ 841 extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 ); 842 extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); 843 extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); 844 extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*, 845 Bool mode64, void* dispatch ); 846 847 extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 848 HReg rreg, Int offsetB, Bool mode64 ); 849 extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 850 HReg rreg, Int offsetB, Bool mode64 ); 851 852 extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); 853 extern HInstrArray* iselSB_PPC ( IRSB*, VexArch, 854 VexArchInfo*, 855 VexAbiInfo* ); 856 857 #endif /* ndef __VEX_HOST_PPC_DEFS_H */ 858 859 /*---------------------------------------------------------------*/ 860 /*--- end host_ppc_defs.h ---*/ 861 /*---------------------------------------------------------------*/ 862
