| /external/llvm/lib/Target/ARM/ |
| ARMAddressingModes.h | 70 //case ISD::ROTL: // Only if imm -> turn into ROTR.
117 // reg [asr|lsl|lsr|ror|rrx] imm
120 // reg, the second is the shift amount (or reg0 if not present or imm). The
121 // third operand encodes the shift opcode and the imm if a reg isn't present.
123 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
124 return ShOp | (Imm << 3);
133 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
134 /// the 8-bit imm value.
135 static inline unsigned getSOImmValImm(unsigned Imm) {
[all...] |
| ARMMCCodeEmitter.cpp | 81 unsigned &Reg, unsigned &Imm,
146 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
451 Imm = SImm;
710 // {20-16} = imm{15-12}
711 // {11-0} = imm{11-0}
774 // {11-7} = imm
806 unsigned Imm = MO1.getImm();
807 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add
[all...] |
| Thumb1RegisterInfo.cpp | 237 // If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
280 // r4 = add sp, imm
281 // r4 = add r4, imm
346 unsigned DestReg, int Imm,
350 bool isSub = Imm < 0;
351 if (isSub) Imm = -Imm;
354 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
355 Imm -= ThisVal
[all...] |
| ARMCodeEmitter.cpp | 352 unsigned getShiftOp(unsigned Imm) const ;
411 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
412 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
[all...] |
| ARMISelLowering.h | 266 virtual bool isLegalICmpImmediate(int64_t Imm) const;
272 virtual bool isLegalAddImmediate(int64_t Imm) const;
344 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| Thumb2SizeReduction.cpp | 490 unsigned Imm = MI->getOperand(2).getImm();
494 if (Imm & 3 || Imm > 1020)
509 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
597 unsigned Imm = MI->getOperand(2).getImm();
599 if (Imm > Limit)
|
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask);
40 void DecodePSHUFMask(unsigned NElts, unsigned Imm,
43 void DecodePSHUFHWMask(unsigned Imm,
46 void DecodePSHUFLWMask(unsigned Imm,
67 void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
|
| X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) {
31 unsigned ZMask = Imm & 15;
32 unsigned CountD = (Imm >> 4) & 3;
33 unsigned CountS = (Imm >> 6) & 3;
66 void DecodePSHUFMask(unsigned NElts, unsigned Imm,
69 ShuffleMask.push_back(Imm % NElts);
70 Imm /= NElts;
74 void DecodePSHUFHWMask(unsigned Imm,
81 ShuffleMask.push_back(4+(Imm & 3));
82 Imm >>= 2
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 inline SDValue getI64Imm(uint64_t Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 inline SDValue getSmallIPtrImm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
105 /// a base register plus a signed 16-bit displacement [r+imm].
121 /// be represented by [r+imm], which are preferred.
133 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
259 static bool isIntS16Immediate(SDNode *N, short &Imm) {
[all...] |
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.h | 23 enum MapKind { Operand, Imm, Reg };
27 uint64_t Imm; // Integer immedate value.
|
| PseudoLoweringEmitter.cpp | 58 OperandMap[BaseIdx + i].Kind = OpData::Imm;
59 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
188 case OpData::Imm:
190 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| CodeGenInstruction.h | 285 int64_t Imm;
294 ResultOperand(int64_t I) : Imm(I), Kind(K_Imm) {}
303 int64_t getImm() const { assert(isImm()); return Imm; }
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 175 uint64_t Imm);
196 uint64_t Imm);
205 uint64_t Imm, MVT ImmType);
213 uint64_t Imm);
259 uint64_t Imm);
284 uint64_t Imm);
290 uint64_t Imm);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
113 return isIntS32Immediate(Op.getNode(), Imm);
119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0
154 int32_t imm = 0; local
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
[all...] |
| MBlazeISelLowering.h | 181 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 103 inline SDValue getI8Imm(uint64_t Imm) {
104 return CurDAG->getTargetConstant(Imm, MVT::i8);
109 inline SDValue getI16Imm(uint64_t Imm) {
110 return CurDAG->getTargetConstant(Imm, MVT::i16);
115 inline SDValue getI32Imm(uint64_t Imm) {
116 return CurDAG->getTargetConstant(Imm, MVT::i32);
159 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
161 Imm = Val;
171 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
173 Imm = Val
[all...] |
| SystemZISelLowering.h | 91 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 365 uint64_t Imm = CI->getZExtValue();
370 isPowerOf2_64(Imm)) {
371 Imm = Log2_64(Imm);
376 Op0IsKill, Imm, VT.getSimpleVT());
[all...] |
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 100 } Imm;
124 Imm = o.Imm;
151 return Imm.Val;
243 Op->Imm.Val = Val;
251 Op->Imm.Val = Val;
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 110 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/valgrind/main/VEX/priv/ |
| host_ppc_defs.c | 392 op->Prh.Imm.syned = syned;
393 op->Prh.Imm.imm16 = imm16;
411 if (op->Prh.Imm.syned)
412 vex_printf("%d", (Int)(Short)op->Prh.Imm.imm16);
414 vex_printf("%u", (UInt)(UShort)op->Prh.Imm.imm16);
457 op->Pri.Imm = imm64;
470 vex_printf("0x%llx", dst->Pri.Imm);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 468 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
470 if (isInt<8>(Imm))
474 if (isInt<8>(Imm))
480 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
482 if (isInt<8>(Imm))
486 if (isInt<8>(Imm))
611 int Imm = (int)(MI.getOperand(i + 3).getImm());
612 int Offset = FIOffset + Imm;
613 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 35 IndirectAddr, ///< D-Form "imm($r)" and X-form "$r($r)"
179 virtual bool isLegalICmpImmediate(int64_t Imm) const;
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 180 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 54 inline SDValue getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
|
