1 //===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines structures to encapsulate information gleaned from the 11 // target register and register class definitions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef CODEGEN_REGISTERS_H 16 #define CODEGEN_REGISTERS_H 17 18 #include "Record.h" 19 #include "SetTheory.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/DenseMap.h" 23 #include "llvm/ADT/SetVector.h" 24 #include <cstdlib> 25 #include <map> 26 #include <string> 27 #include <set> 28 #include <vector> 29 30 namespace llvm { 31 class CodeGenRegBank; 32 33 /// CodeGenRegister - Represents a register definition. 34 struct CodeGenRegister { 35 Record *TheDef; 36 unsigned EnumValue; 37 unsigned CostPerUse; 38 39 // Map SubRegIndex -> Register. 40 typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap; 41 42 CodeGenRegister(Record *R, unsigned Enum); 43 44 const std::string &getName() const; 45 46 // Get a map of sub-registers computed lazily. 47 // This includes unique entries for all sub-sub-registers. 48 const SubRegMap &getSubRegs(CodeGenRegBank&); 49 50 const SubRegMap &getSubRegs() const { 51 assert(SubRegsComplete && "Must precompute sub-registers"); 52 return SubRegs; 53 } 54 55 // Add sub-registers to OSet following a pre-order defined by the .td file. 56 void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const; 57 58 // List of super-registers in topological order, small to large. 59 typedef std::vector<CodeGenRegister*> SuperRegList; 60 61 // Get the list of super-registers. 62 // This is only valid after computeDerivedInfo has visited all registers. 63 const SuperRegList &getSuperRegs() const { 64 assert(SubRegsComplete && "Must precompute sub-registers"); 65 return SuperRegs; 66 } 67 68 // Order CodeGenRegister pointers by EnumValue. 69 struct Less { 70 bool operator()(const CodeGenRegister *A, 71 const CodeGenRegister *B) const { 72 return A->EnumValue < B->EnumValue; 73 } 74 }; 75 76 // Canonically ordered set. 77 typedef std::set<const CodeGenRegister*, Less> Set; 78 79 private: 80 bool SubRegsComplete; 81 SubRegMap SubRegs; 82 SuperRegList SuperRegs; 83 }; 84 85 86 class CodeGenRegisterClass { 87 CodeGenRegister::Set Members; 88 const std::vector<Record*> *Elements; 89 std::vector<SmallVector<Record*, 16> > AltOrders; 90 public: 91 Record *TheDef; 92 std::string Namespace; 93 std::vector<MVT::SimpleValueType> VTs; 94 unsigned SpillSize; 95 unsigned SpillAlignment; 96 int CopyCost; 97 bool Allocatable; 98 // Map SubRegIndex -> RegisterClass 99 DenseMap<Record*,Record*> SubRegClasses; 100 std::string AltOrderSelect; 101 102 const std::string &getName() const; 103 const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;} 104 unsigned getNumValueTypes() const { return VTs.size(); } 105 106 MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { 107 if (VTNum < VTs.size()) 108 return VTs[VTNum]; 109 assert(0 && "VTNum greater than number of ValueTypes in RegClass!"); 110 abort(); 111 } 112 113 // Return true if this this class contains the register. 114 bool contains(const CodeGenRegister*) const; 115 116 // Returns true if RC is a subclass. 117 // RC is a sub-class of this class if it is a valid replacement for any 118 // instruction operand where a register of this classis required. It must 119 // satisfy these conditions: 120 // 121 // 1. All RC registers are also in this. 122 // 2. The RC spill size must not be smaller than our spill size. 123 // 3. RC spill alignment must be compatible with ours. 124 // 125 bool hasSubClass(const CodeGenRegisterClass *RC) const; 126 127 // Returns an ordered list of class members. 128 // The order of registers is the same as in the .td file. 129 // No = 0 is the default allocation order, No = 1 is the first alternative. 130 ArrayRef<Record*> getOrder(unsigned No = 0) const { 131 if (No == 0) 132 return *Elements; 133 else 134 return AltOrders[No - 1]; 135 } 136 137 // Return the total number of allocation orders available. 138 unsigned getNumOrders() const { return 1 + AltOrders.size(); } 139 140 CodeGenRegisterClass(CodeGenRegBank&, Record *R); 141 }; 142 143 // CodeGenRegBank - Represent a target's registers and the relations between 144 // them. 145 class CodeGenRegBank { 146 RecordKeeper &Records; 147 SetTheory Sets; 148 149 std::vector<Record*> SubRegIndices; 150 unsigned NumNamedIndices; 151 std::vector<CodeGenRegister*> Registers; 152 DenseMap<Record*, CodeGenRegister*> Def2Reg; 153 154 std::vector<CodeGenRegisterClass> RegClasses; 155 DenseMap<Record*, CodeGenRegisterClass*> Def2RC; 156 157 // Composite SubRegIndex instances. 158 // Map (SubRegIndex, SubRegIndex) -> SubRegIndex. 159 typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap; 160 CompositeMap Composite; 161 162 // Populate the Composite map from sub-register relationships. 163 void computeComposites(); 164 165 public: 166 CodeGenRegBank(RecordKeeper&); 167 168 SetTheory &getSets() { return Sets; } 169 170 // Sub-register indices. The first NumNamedIndices are defined by the user 171 // in the .td files. The rest are synthesized such that all sub-registers 172 // have a unique name. 173 const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; } 174 unsigned getNumNamedIndices() { return NumNamedIndices; } 175 176 // Map a SubRegIndex Record to its enum value. 177 unsigned getSubRegIndexNo(Record *idx); 178 179 // Find or create a sub-register index representing the A+B composition. 180 Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false); 181 182 const std::vector<CodeGenRegister*> &getRegisters() { return Registers; } 183 184 // Find a register from its Record def. 185 CodeGenRegister *getReg(Record*); 186 187 const std::vector<CodeGenRegisterClass> &getRegClasses() { 188 return RegClasses; 189 } 190 191 // Find a register class from its def. 192 CodeGenRegisterClass *getRegClass(Record*); 193 194 /// getRegisterClassForRegister - Find the register class that contains the 195 /// specified physical register. If the register is not in a register 196 /// class, return null. If the register is in multiple classes, and the 197 /// classes have a superset-subset relationship and the same set of types, 198 /// return the superclass. Otherwise return null. 199 const CodeGenRegisterClass* getRegClassForRegister(Record *R); 200 201 // Computed derived records such as missing sub-register indices. 202 void computeDerivedInfo(); 203 204 // Compute full overlap sets for every register. These sets include the 205 // rarely used aliases that are neither sub nor super-registers. 206 // 207 // Map[R1].count(R2) is reflexive and symmetric, but not transitive. 208 // 209 // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2]. 210 void computeOverlaps(std::map<const CodeGenRegister*, 211 CodeGenRegister::Set> &Map); 212 }; 213 } 214 215 #endif 216
