| /external/valgrind/main/none/tests/ |
| pth_once.stdout.exp | 2 identify_yourself: Hi, I'm a thread
3 identify_yourself: Hi, I'm a thread
4 identify_yourself: Hi, I'm a thread
5 identify_yourself: Hi, I'm a thread
6 identify_yourself: Hi, I'm a thread
7 identify_yourself: Hi, I'm a thread
8 identify_yourself: Hi, I'm a thread
9 identify_yourself: Hi, I'm a thread
10 identify_yourself: Hi, I'm a thread
11 identify_yourself: Hi, I'm a threa
[all...] |
| /external/valgrind/main/drd/tests/ |
| tc21_pthonce.stdout.exp | 2 child: Hi, I'm thread 0
3 child: Hi, I'm thread 1
|
| /external/valgrind/main/helgrind/tests/ |
| tc21_pthonce.stdout.exp | 2 child: Hi, I'm thread 0
3 child: Hi, I'm thread 1
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.h | 152 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
163 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
165 SDValue &Lo, SDValue &Hi);
283 /// of Op are exactly equal to the bits of Lo; the high bits exactly equal Hi.
286 /// Op, and Hi being equal to the upper 32 bits.
287 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
288 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
292 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
293 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
294 void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
[all...] |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
31 // These routines assume that the Lo/Hi part is stored first in memory on
32 // little/big-endian machines, followed by the Hi/Lo part. This means that
35 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
51 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
53 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
58 GetExpandedOp(InOp, Lo, Hi);
60 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 211 SDValue Lo, Hi;
212 GetSplitVector(N->getOperand(0), Lo, Hi);
214 Hi = BitConvertToInteger(Hi);
217 std::swap(Lo, Hi);
222 JoinIntegers(Lo, Hi));
617 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
619 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
620 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
[all...] |
| LegalizeVectorTypes.cpp | 407 SDValue Lo, Hi;
418 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
419 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
420 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
421 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
422 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
423 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
424 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
425 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
426 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| LegalizeTypes.cpp | 765 SDValue &Hi) {
771 Hi = Entry.second;
775 SDValue Hi) {
778 Hi.getValueType() == Lo.getValueType() &&
780 // Lo/Hi may have been newly allocated, if so, add nodeid's as relevant.
782 AnalyzeNewValue(Hi);
788 Entry.second = Hi;
792 SDValue &Hi) {
798 Hi = Entry.second;
802 SDValue Hi) {
[all...] |
| /external/llvm/include/llvm/Support/ |
| SwapByteOrder.h | 33 uint16_t Hi = value << 8;
35 return Hi | Lo;
65 uint64_t Hi = SwapByteOrder_32(uint32_t(value));
67 return (Hi << 32) | Lo;
|
| MathExtras.h | 204 // get hi portion
205 uint32_t Hi = Hi_32(Value);
207 // if some bits in hi portion
208 if (Hi) {
209 // leading zeros in hi portion plus all bits in lo portion
210 Count = CountLeadingZeros_32(Hi);
|
| /frameworks/media/libvideoeditor/vss/3gpwriter/inc/ |
| M4MP4W_Utils.h | 96 * Put Hi and Lo u16 part in a u32 variable
99 M4OSA_Void M4MP4W_put32_Hi(M4OSA_UInt32* tab, M4OSA_UInt16 Hi);
|
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | 830 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
839 /// \param Hi - The classification for the parts of the type
842 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
850 /// \param Hi - The classification for the parts of the type
863 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
865 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi) const;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| AsmPrinter.h | 331 /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size
332 /// in bytes of the directive is specified by Size and Hi/Lo specify the
334 void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo,
337 /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo"
338 /// where the size in bytes of the directive is specified by Size and Hi/Lo
340 void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset,
|
| /external/webkit/Tools/Scripts/webkitpy/tool/bot/ |
| irc_command.py | 106 class Hi(IRCCommand):
141 "hi": Hi,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 469 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
500 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
704 // Custom legalize GlobalAddress nodes into LO/HI parts.
817 case SPISD::Hi: return "SPISD::Hi";
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 557 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
560 SDValue Lo(Hi.getNode(), 1);
561 SDValue Ops[] = { Lo, Hi };
574 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
577 SDValue Lo(Hi.getNode(), 1);
578 SDValue Ops[] = { Lo, Hi };
671 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
674 SDValue Lo(Hi.getNode(), 1);
675 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
679 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl
[all...] |
| /external/llvm/lib/MC/ |
| SubtargetFeature.cpp | 127 const T *Hi = A + L;
129 const T *F = std::lower_bound(A, Hi, KV);
131 if (F == Hi || StringRef(F->Key) != S) return NULL;
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DIE.h | 341 DIEDelta(const MCSymbol *Hi, const MCSymbol *Lo)
342 : DIEValue(isDelta), LabelHi(Hi), LabelLo(Lo) {}
|
| /frameworks/media/libvideoeditor/vss/3gpwriter/src/ |
| M4MP4W_Utils.c | 281 M4OSA_Void M4MP4W_put32_Hi(M4OSA_UInt32* tab, M4OSA_UInt16 Hi)
285 *tab |= Hi<<16;
|
| /external/skia/src/core/ |
| SkMath.cpp | 110 int32_t hi = A + (B >> 16) + (lo < C); local
113 hi = -hi - Sk32ToBool(lo);
119 SkASSERT(((int32_t)lo >> 31) == hi);
123 return hi >> (shift - 32);
126 int32_t tmp = hi >> shift;
129 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
131 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit;
190 uint32_t Hi = A + (B >>16) + (Lo < C);
192 SkASSERT((Hi >> 29) == 0); // else overflo
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.h | 31 Hi, ///< High address component (upper 16)
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 33 // No relation with Mips Hi register
34 Hi,
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 195 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI,
197 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
603 SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
605 SDValue Ops[2] = { Lo, Hi };
640 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI,
642 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
657 SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA,
659 SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
[all...] |
