/external/llvm/lib/Target/MBlaze/ |
MBlazeAsmBackend.cpp | 76 case MBlaze::ORI: return MBlaze::ORI32;
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/external/v8/src/mips/ |
constants-mips.cc | 315 case ORI:
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assembler-mips-inl.h | 106 // For an instructions like LUI/ORI where the target bits are mixed into the 113 // address of the instruction that follows LUI/ORI instruction pair. 238 (instr1 & kOpcodeMask) == ORI &&
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assembler-mips.cc | 146 // specially coded on MIPS means that it is a lui/ori instruction, and that is 1183 void Assembler::ori(Register rt, Register rs, int32_t j) { function in class:v8::internal::Assembler [all...] |
constants-mips.h | 214 ORI = ((1 << 3) + 5) << kOpcodeShift,
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simulator-mips.cc | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 97 // transform this into the appropriate ORI instruction. 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 379 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 592 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 670 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; [all...] |
PPCRegisterInfo.cpp | 336 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 648 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
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PPCISelLowering.cpp | [all...] |
/external/qemu/tcg/ppc64/ |
tcg-target.c | 305 #define ORI OPCD( 24) 457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16); [all...] |
/external/qemu/tcg/ppc/ |
tcg-target.c | 317 #define ORI OPCD(24) 453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); [all...] |
/external/icu4c/common/ |
ucnvisci.c | 94 ORI = 0x47, 147 { ORIYA, ORI_MASK, ORI }, 270 * | DEV | PNJ | GJR | ORI | BNG | TLG | MLM | TML | [all...] |
/external/llvm/lib/Target/MBlaze/Disassembler/ |
MBlazeDisassembler.cpp | 53 MBlaze::ORI, MBlaze::ANDI, MBlaze::XORI, MBlaze::ANDNI, //28,29,2A,2B
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/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | [all...] |