| /external/llvm/lib/CodeGen/ |
| RegAllocBase.h | 85 LiveIntervalUnion& operator[](unsigned PhysReg) {
86 assert(PhysReg < NumRegs && "physReg out of bounds");
87 return Array[PhysReg];
98 // Current queries, one per physreg. They must be reinitialized each time we
113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
114 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
115 return Queries[PhysReg];
140 // Each call must guarantee forward progess by returning an available PhysReg
[all...] |
| RegisterClassInfo.h | 91 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
92 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
93 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
94 if (unsigned N = CSRNum[PhysReg])
99 /// isReserved - Returns true when PhysReg is a reserved register.
104 bool isReserved(unsigned PhysReg) const {
105 return Reserved.test(PhysReg);
108 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
114 bool isAllocatable(unsigned PhysReg) const {
115 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg)
[all...] |
| AllocationOrder.h | 67 /// isHint - Return true if PhysReg is a preferred register.
68 bool isHint(unsigned PhysReg) const { return PhysReg == Hint; }
|
| RegAllocFast.cpp | 74 unsigned PhysReg; // Currently held here.
78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161 unsigned calcSpillCost(unsigned PhysReg) const;
162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
216 if (MO.getReg() == LR.PhysReg)
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
228 PhysRegState[LR.PhysReg] = regFree
[all...] |
| InterferenceCache.h | 37 /// of PhysReg in all basic blocks.
39 /// PhysReg - The register currently represented.
40 unsigned PhysReg;
59 /// PhysReg.
74 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {}
78 PhysReg = 0;
83 unsigned getPhysReg() const { return PhysReg; }
91 /// valid - Return true if this is a valid entry for physReg.
94 /// reset - Initialize entry to represent physReg's aliases.
95 void reset(unsigned physReg,
[all...] |
| RegisterClassInfo.cpp | 86 unsigned PhysReg = RawOrder[i];
88 if (Reserved.test(PhysReg))
90 if (CSRNum[PhysReg])
91 // PhysReg aliases a CSR, save it for later.
92 CSRAlias.push_back(PhysReg);
94 RCI.Order[N++] = PhysReg;
|
| RegAllocBasic.cpp | 190 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) {
191 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI));
192 LiveVirtRegBitSet &VRegs = unionVRegs[PhysReg];
193 PhysReg2LiveUnion[PhysReg].verify(VRegs);
206 unsigned PhysReg = VRM->getPhys(reg);
207 if (!unionVRegs[PhysReg].test(reg)) {
209 TRI->getName(PhysReg) << "\n";
277 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
[all...] |
| VirtRegRewriter.cpp | 169 // indicating which stack slot values are currently held by a physreg. This
171 // physreg is modified.
174 void disallowClobberPhysRegOnly(unsigned PhysReg);
176 void ClobberPhysRegOnly(unsigned PhysReg);
191 /// available in a physical register, return that PhysReg, otherwise
203 /// in the specified physreg. If CanClobber is true, the physreg can be
206 // If this stack slot is thought to be available in some other physreg,
219 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg)
225 /// specified stack slot must be available in a physreg for this query t
[all...] |
| RegAllocGreedy.cpp | 160 unsigned PhysReg;
166 PhysReg = Reg;
173 /// Candidate info for for each PhysReg in AllocationOrder.
307 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
308 unassign(LIS->getInterval(VirtReg), PhysReg);
317 unsigned PhysReg = VRM->getPhys(VirtReg);
318 if (!PhysReg)
323 unassign(LI, PhysReg);
391 unsigned PhysReg;
392 while ((PhysReg = Order.next())
[all...] |
| InterferenceCache.cpp | 33 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
34 unsigned E = PhysRegEntries[PhysReg];
35 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
51 Entries[E].reset(PhysReg, LIUArray, TRI, MF);
52 PhysRegEntries[PhysReg] = E;
68 void InterferenceCache::Entry::reset(unsigned physReg,
75 PhysReg = physReg;
78 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS) {
94 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS, ++i)
[all...] |
| VirtRegMap.cpp | 119 unsigned physReg = Hint.second;
120 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
121 physReg = getPhys(physReg);
123 return (TargetRegisterInfo::isPhysicalRegister(physReg))
124 ? physReg : 0;
125 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
282 unsigned PhysReg = getPhys(VirtReg);
283 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg")
[all...] |
| VirtRegMap.h | 184 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
186 TargetRegisterInfo::isPhysicalRegister(physReg));
190 Virt2PhysMap[virtReg] = physReg;
211 /// @brief returns true if VirtReg is assigned to its preferred physreg.
389 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
391 EmergencySpillMap[MI].push_back(PhysReg);
394 PhysRegs.push_back(PhysReg);
|
| LiveIntervalAnalysis.cpp | 201 unsigned PhysReg = mop.getReg();
202 if (PhysReg == 0 || PhysReg == li.reg)
204 if (TargetRegisterInfo::isVirtualRegister(PhysReg)) {
205 if (!vrm.hasPhys(PhysReg))
207 PhysReg = vrm.getPhys(PhysReg);
209 if (PhysReg && tri_->regsOverlap(PhysReg, reg))
236 unsigned PhysReg = MO.getReg()
[all...] |
| RegAllocLinearScan.cpp | 314 void addRegUse(unsigned physReg) {
315 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
317 ++regUse_[physReg];
318 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
322 void delRegUse(unsigned physReg) {
323 assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
325 assert(regUse_[physReg] != 0);
326 --regUse_[physReg];
327 for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
333 bool isRegAvail(unsigned physReg) const
[all...] |
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 399 std::string PhysReg;
402 return PhysReg;
407 return PhysReg;
409 PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
411 PhysReg += "::";
412 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
413 return PhysReg;
515 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
516 if (PhysReg.empty()) {
526 PhysRegInputs->push_back(PhysReg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 105 unsigned &PhysReg, int &Cost) {
118 PhysReg = Reg;
428 unsigned PhysReg = 0;
431 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
432 assert((PhysReg == 0 || !isChain) &&
433 "Chain dependence via physreg data?");
440 PhysReg = 0;
449 OpLatency, PhysReg);
|
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalAnalysis.h | 286 unsigned PhysReg, VirtRegMap &vrm);
307 unsigned PhysReg) const;
|
