| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR,
375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
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| MSP430ISelLowering.cpp | 97 setOperationAction(ISD::SRA, MVT::i8, Custom);
100 setOperationAction(ISD::SRA, MVT::i16, Custom);
183 case ISD::SRA: return LowerShifts(Op, DAG);
606 case ISD::SRA:
607 return DAG.getNode(MSP430ISD::SRA, dl,
826 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
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| /external/v8/src/mips/ |
| constants-mips.cc | 244 case SRA:
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| constants-mips.h | 251 SRA = ((0 << 3) + 3),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 71 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
508 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
737 case ISD::SRA:
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| DAGCombiner.cpp | 836 if (Opc == ISD::SRA)
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| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
152 case ISD::SRA:
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| FastISel.cpp | 367 // Transform "sdiv exact X, 8" -> "sra X, 3".
372 ISDOpcode = ISD::SRA;
902 return SelectBinaryOp(I, ISD::SRA);
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| SelectionDAGBuilder.h | 477 void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
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| SelectionDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::SRA:
488 case ISD::SRA:
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| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAddressingModes.h | 68 case ISD::SRA: return ARM_AM::asr;
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| ARMISelLowering.cpp | 125 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
500 setTargetDAGCombine(ISD::SRA);
552 setOperationAction(ISD::SRA, MVT::i64, Custom);
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
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| PPCISelLowering.cpp | 438 case PPCISD::SRA: return "PPCISD::SRA";
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| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 245 setOperationAction(ISD::SRA, MVT::i8, Custom);
250 setOperationAction(ISD::SRA, MVT::i64, Legal);
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| SPUISelDAGToDAG.cpp | 236 //! Emit the instruction sequence for i64 sra
753 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
756 // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
792 } else if (Opc == ISD::SRA) {
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| /external/llvm/utils/TableGen/ |
| Record.cpp | 733 case SRA:
743 case SRA: Result = LHSv >> RHSv; break;
768 case SRA: Result = "!sra"; break;
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| Record.h | [all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 126 case 0x01: return MBlaze::SRA;
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 264 // sra dst, dst
320 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
444 // sra dst, dst
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| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 481 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
737 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
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