1 #ifndef _LINUX_SPI_CPCAP_H 2 #define _LINUX_SPI_CPCAP_H 3 4 /* 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 17 * 02111-1307, USA 18 * 19 */ 20 21 #include <linux/ioctl.h> 22 #ifdef __KERNEL__ 23 #include <linux/workqueue.h> 24 #include <linux/completion.h> 25 #include <linux/power_supply.h> 26 #include <linux/platform_device.h> 27 #endif 28 29 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD 30 #include <linux/rtc.h> 31 #endif 32 33 #define CPCAP_DEV_NAME "cpcap" 34 #define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1) 35 36 #define CPCAP_IRQ_INT1_INDEX 0 37 #define CPCAP_IRQ_INT2_INDEX 16 38 #define CPCAP_IRQ_INT3_INDEX 32 39 #define CPCAP_IRQ_INT4_INDEX 48 40 #define CPCAP_IRQ_INT5_INDEX 64 41 42 #define CPCAP_HWCFG_NUM 2 /* The number of hardware config words. */ 43 /* 44 * Tell the uC to setup the secondary standby bits for the regulators used. 45 */ 46 #define CPCAP_HWCFG0_SEC_STBY_SW1 0x0001 47 #define CPCAP_HWCFG0_SEC_STBY_SW2 0x0002 48 #define CPCAP_HWCFG0_SEC_STBY_SW3 0x0004 49 #define CPCAP_HWCFG0_SEC_STBY_SW4 0x0008 50 #define CPCAP_HWCFG0_SEC_STBY_SW5 0x0010 51 #define CPCAP_HWCFG0_SEC_STBY_VAUDIO 0x0020 52 #define CPCAP_HWCFG0_SEC_STBY_VCAM 0x0040 53 #define CPCAP_HWCFG0_SEC_STBY_VCSI 0x0080 54 #define CPCAP_HWCFG0_SEC_STBY_VDAC 0x0100 55 #define CPCAP_HWCFG0_SEC_STBY_VDIG 0x0200 56 #define CPCAP_HWCFG0_SEC_STBY_VHVIO 0x0400 57 #define CPCAP_HWCFG0_SEC_STBY_VPLL 0x0800 58 #define CPCAP_HWCFG0_SEC_STBY_VRF1 0x1000 59 #define CPCAP_HWCFG0_SEC_STBY_VRF2 0x2000 60 #define CPCAP_HWCFG0_SEC_STBY_VRFREF 0x4000 61 #define CPCAP_HWCFG0_SEC_STBY_VSDIO 0x8000 62 63 #define CPCAP_HWCFG1_SEC_STBY_VWLAN1 0x0001 64 #define CPCAP_HWCFG1_SEC_STBY_VWLAN2 0x0002 65 #define CPCAP_HWCFG1_SEC_STBY_VSIM 0x0004 66 #define CPCAP_HWCFG1_SEC_STBY_VSIMCARD 0x0008 67 68 #define CPCAP_WHISPER_MODE_PU 0x00000001 69 #define CPCAP_WHISPER_ENABLE_UART 0x00000002 70 #define CPCAP_WHISPER_ACCY_MASK 0xF8000000 71 #define CPCAP_WHISPER_ACCY_SHFT 27 72 #define CPCAP_WHISPER_ID_SIZE 16 73 #define CPCAP_WHISPER_PROP_SIZE 7 74 75 enum cpcap_regulator_id { 76 CPCAP_SW2, 77 CPCAP_SW4, 78 CPCAP_SW5, 79 CPCAP_VCAM, 80 CPCAP_VCSI, 81 CPCAP_VDAC, 82 CPCAP_VDIG, 83 CPCAP_VFUSE, 84 CPCAP_VHVIO, 85 CPCAP_VSDIO, 86 CPCAP_VPLL, 87 CPCAP_VRF1, 88 CPCAP_VRF2, 89 CPCAP_VRFREF, 90 CPCAP_VWLAN1, 91 CPCAP_VWLAN2, 92 CPCAP_VSIM, 93 CPCAP_VSIMCARD, 94 CPCAP_VVIB, 95 CPCAP_VUSB, 96 CPCAP_VAUDIO, 97 CPCAP_NUM_REGULATORS 98 }; 99 100 /* 101 * Enumeration of all registers in the cpcap. Note that the register 102 * numbers on the CPCAP IC are not contiguous. The values of the enums below 103 * are not the actual register numbers. 104 */ 105 enum cpcap_reg { 106 CPCAP_REG_START, /* Start of CPCAP registers. */ 107 108 CPCAP_REG_INT1 = CPCAP_REG_START, /* Interrupt 1 */ 109 CPCAP_REG_INT2, /* Interrupt 2 */ 110 CPCAP_REG_INT3, /* Interrupt 3 */ 111 CPCAP_REG_INT4, /* Interrupt 4 */ 112 CPCAP_REG_INTM1, /* Interrupt Mask 1 */ 113 CPCAP_REG_INTM2, /* Interrupt Mask 2 */ 114 CPCAP_REG_INTM3, /* Interrupt Mask 3 */ 115 CPCAP_REG_INTM4, /* Interrupt Mask 4 */ 116 CPCAP_REG_INTS1, /* Interrupt Sense 1 */ 117 CPCAP_REG_INTS2, /* Interrupt Sense 2 */ 118 CPCAP_REG_INTS3, /* Interrupt Sense 3 */ 119 CPCAP_REG_INTS4, /* Interrupt Sense 4 */ 120 CPCAP_REG_ASSIGN1, /* Resource Assignment 1 */ 121 CPCAP_REG_ASSIGN2, /* Resource Assignment 2 */ 122 CPCAP_REG_ASSIGN3, /* Resource Assignment 3 */ 123 CPCAP_REG_ASSIGN4, /* Resource Assignment 4 */ 124 CPCAP_REG_ASSIGN5, /* Resource Assignment 5 */ 125 CPCAP_REG_ASSIGN6, /* Resource Assignment 6 */ 126 CPCAP_REG_VERSC1, /* Version Control 1 */ 127 CPCAP_REG_VERSC2, /* Version Control 2 */ 128 129 CPCAP_REG_MI1, /* Macro Interrupt 1 */ 130 CPCAP_REG_MIM1, /* Macro Interrupt Mask 1 */ 131 CPCAP_REG_MI2, /* Macro Interrupt 2 */ 132 CPCAP_REG_MIM2, /* Macro Interrupt Mask 2 */ 133 CPCAP_REG_UCC1, /* UC Control 1 */ 134 CPCAP_REG_UCC2, /* UC Control 2 */ 135 CPCAP_REG_PC1, /* Power Cut 1 */ 136 CPCAP_REG_PC2, /* Power Cut 2 */ 137 CPCAP_REG_BPEOL, /* BP and EOL */ 138 CPCAP_REG_PGC, /* Power Gate and Control */ 139 CPCAP_REG_MT1, /* Memory Transfer 1 */ 140 CPCAP_REG_MT2, /* Memory Transfer 2 */ 141 CPCAP_REG_MT3, /* Memory Transfer 3 */ 142 CPCAP_REG_PF, /* Print Format */ 143 144 CPCAP_REG_SCC, /* System Clock Control */ 145 CPCAP_REG_SW1, /* Stop Watch 1 */ 146 CPCAP_REG_SW2, /* Stop Watch 2 */ 147 CPCAP_REG_UCTM, /* UC Turbo Mode */ 148 CPCAP_REG_TOD1, /* Time of Day 1 */ 149 CPCAP_REG_TOD2, /* Time of Day 2 */ 150 CPCAP_REG_TODA1, /* Time of Day Alarm 1 */ 151 CPCAP_REG_TODA2, /* Time of Day Alarm 2 */ 152 CPCAP_REG_DAY, /* Day */ 153 CPCAP_REG_DAYA, /* Day Alarm */ 154 CPCAP_REG_VAL1, /* Validity 1 */ 155 CPCAP_REG_VAL2, /* Validity 2 */ 156 157 CPCAP_REG_SDVSPLL, /* Switcher DVS and PLL */ 158 CPCAP_REG_SI2CC1, /* Switcher I2C Control 1 */ 159 CPCAP_REG_Si2CC2, /* Switcher I2C Control 2 */ 160 CPCAP_REG_S1C1, /* Switcher 1 Control 1 */ 161 CPCAP_REG_S1C2, /* Switcher 1 Control 2 */ 162 CPCAP_REG_S2C1, /* Switcher 2 Control 1 */ 163 CPCAP_REG_S2C2, /* Switcher 2 Control 2 */ 164 CPCAP_REG_S3C, /* Switcher 3 Control */ 165 CPCAP_REG_S4C1, /* Switcher 4 Control 1 */ 166 CPCAP_REG_S4C2, /* Switcher 4 Control 2 */ 167 CPCAP_REG_S5C, /* Switcher 5 Control */ 168 CPCAP_REG_S6C, /* Switcher 6 Control */ 169 CPCAP_REG_VCAMC, /* VCAM Control */ 170 CPCAP_REG_VCSIC, /* VCSI Control */ 171 CPCAP_REG_VDACC, /* VDAC Control */ 172 CPCAP_REG_VDIGC, /* VDIG Control */ 173 CPCAP_REG_VFUSEC, /* VFUSE Control */ 174 CPCAP_REG_VHVIOC, /* VHVIO Control */ 175 CPCAP_REG_VSDIOC, /* VSDIO Control */ 176 CPCAP_REG_VPLLC, /* VPLL Control */ 177 CPCAP_REG_VRF1C, /* VRF1 Control */ 178 CPCAP_REG_VRF2C, /* VRF2 Control */ 179 CPCAP_REG_VRFREFC, /* VRFREF Control */ 180 CPCAP_REG_VWLAN1C, /* VWLAN1 Control */ 181 CPCAP_REG_VWLAN2C, /* VWLAN2 Control */ 182 CPCAP_REG_VSIMC, /* VSIM Control */ 183 CPCAP_REG_VVIBC, /* VVIB Control */ 184 CPCAP_REG_VUSBC, /* VUSB Control */ 185 CPCAP_REG_VUSBINT1C, /* VUSBINT1 Control */ 186 CPCAP_REG_VUSBINT2C, /* VUSBINT2 Control */ 187 CPCAP_REG_URT, /* Useroff Regulator Trigger */ 188 CPCAP_REG_URM1, /* Useroff Regulator Mask 1 */ 189 CPCAP_REG_URM2, /* Useroff Regulator Mask 2 */ 190 191 CPCAP_REG_VAUDIOC, /* VAUDIO Control */ 192 CPCAP_REG_CC, /* Codec Control */ 193 CPCAP_REG_CDI, /* Codec Digital Interface */ 194 CPCAP_REG_SDAC, /* Stereo DAC */ 195 CPCAP_REG_SDACDI, /* Stereo DAC Digital Interface */ 196 CPCAP_REG_TXI, /* TX Inputs */ 197 CPCAP_REG_TXMP, /* TX MIC PGA's */ 198 CPCAP_REG_RXOA, /* RX Output Amplifiers */ 199 CPCAP_REG_RXVC, /* RX Volume Control */ 200 CPCAP_REG_RXCOA, /* RX Codec to Output Amps */ 201 CPCAP_REG_RXSDOA, /* RX Stereo DAC to Output Amps */ 202 CPCAP_REG_RXEPOA, /* RX External PGA to Output Amps */ 203 CPCAP_REG_RXLL, /* RX Low Latency */ 204 CPCAP_REG_A2LA, /* A2 Loudspeaker Amplifier */ 205 CPCAP_REG_MIPIS1, /* MIPI Slimbus 1 */ 206 CPCAP_REG_MIPIS2, /* MIPI Slimbus 2 */ 207 CPCAP_REG_MIPIS3, /* MIPI Slimbus 3. */ 208 CPCAP_REG_LVAB, /* LMR Volume and A4 Balanced. */ 209 210 CPCAP_REG_CCC1, /* Coulomb Counter Control 1 */ 211 CPCAP_REG_CRM, /* Charger and Reverse Mode */ 212 CPCAP_REG_CCCC2, /* Coincell and Coulomb Ctr Ctrl 2 */ 213 CPCAP_REG_CCS1, /* Coulomb Counter Sample 1 */ 214 CPCAP_REG_CCS2, /* Coulomb Counter Sample 2 */ 215 CPCAP_REG_CCA1, /* Coulomb Counter Accumulator 1 */ 216 CPCAP_REG_CCA2, /* Coulomb Counter Accumulator 2 */ 217 CPCAP_REG_CCM, /* Coulomb Counter Mode */ 218 CPCAP_REG_CCO, /* Coulomb Counter Offset */ 219 CPCAP_REG_CCI, /* Coulomb Counter Integrator */ 220 221 CPCAP_REG_ADCC1, /* A/D Converter Configuration 1 */ 222 CPCAP_REG_ADCC2, /* A/D Converter Configuration 2 */ 223 CPCAP_REG_ADCD0, /* A/D Converter Data 0 */ 224 CPCAP_REG_ADCD1, /* A/D Converter Data 1 */ 225 CPCAP_REG_ADCD2, /* A/D Converter Data 2 */ 226 CPCAP_REG_ADCD3, /* A/D Converter Data 3 */ 227 CPCAP_REG_ADCD4, /* A/D Converter Data 4 */ 228 CPCAP_REG_ADCD5, /* A/D Converter Data 5 */ 229 CPCAP_REG_ADCD6, /* A/D Converter Data 6 */ 230 CPCAP_REG_ADCD7, /* A/D Converter Data 7 */ 231 CPCAP_REG_ADCAL1, /* A/D Converter Calibration 1 */ 232 CPCAP_REG_ADCAL2, /* A/D Converter Calibration 2 */ 233 234 CPCAP_REG_USBC1, /* USB Control 1 */ 235 CPCAP_REG_USBC2, /* USB Control 2 */ 236 CPCAP_REG_USBC3, /* USB Control 3 */ 237 CPCAP_REG_UVIDL, /* ULPI Vendor ID Low */ 238 CPCAP_REG_UVIDH, /* ULPI Vendor ID High */ 239 CPCAP_REG_UPIDL, /* ULPI Product ID Low */ 240 CPCAP_REG_UPIDH, /* ULPI Product ID High */ 241 CPCAP_REG_UFC1, /* ULPI Function Control 1 */ 242 CPCAP_REG_UFC2, /* ULPI Function Control 2 */ 243 CPCAP_REG_UFC3, /* ULPI Function Control 3 */ 244 CPCAP_REG_UIC1, /* ULPI Interface Control 1 */ 245 CPCAP_REG_UIC2, /* ULPI Interface Control 2 */ 246 CPCAP_REG_UIC3, /* ULPI Interface Control 3 */ 247 CPCAP_REG_USBOTG1, /* USB OTG Control 1 */ 248 CPCAP_REG_USBOTG2, /* USB OTG Control 2 */ 249 CPCAP_REG_USBOTG3, /* USB OTG Control 3 */ 250 CPCAP_REG_UIER1, /* USB Interrupt Enable Rising 1 */ 251 CPCAP_REG_UIER2, /* USB Interrupt Enable Rising 2 */ 252 CPCAP_REG_UIER3, /* USB Interrupt Enable Rising 3 */ 253 CPCAP_REG_UIEF1, /* USB Interrupt Enable Falling 1 */ 254 CPCAP_REG_UIEF2, /* USB Interrupt Enable Falling 1 */ 255 CPCAP_REG_UIEF3, /* USB Interrupt Enable Falling 1 */ 256 CPCAP_REG_UIS, /* USB Interrupt Status */ 257 CPCAP_REG_UIL, /* USB Interrupt Latch */ 258 CPCAP_REG_USBD, /* USB Debug */ 259 CPCAP_REG_SCR1, /* Scratch 1 */ 260 CPCAP_REG_SCR2, /* Scratch 2 */ 261 CPCAP_REG_SCR3, /* Scratch 3 */ 262 CPCAP_REG_VMC, /* Video Mux Control */ 263 CPCAP_REG_OWDC, /* One Wire Device Control */ 264 CPCAP_REG_GPIO0, /* GPIO 0 Control */ 265 CPCAP_REG_GPIO1, /* GPIO 1 Control */ 266 CPCAP_REG_GPIO2, /* GPIO 2 Control */ 267 CPCAP_REG_GPIO3, /* GPIO 3 Control */ 268 CPCAP_REG_GPIO4, /* GPIO 4 Control */ 269 CPCAP_REG_GPIO5, /* GPIO 5 Control */ 270 CPCAP_REG_GPIO6, /* GPIO 6 Control */ 271 272 CPCAP_REG_MDLC, /* Main Display Lighting Control */ 273 CPCAP_REG_KLC, /* Keypad Lighting Control */ 274 CPCAP_REG_ADLC, /* Aux Display Lighting Control */ 275 CPCAP_REG_REDC, /* Red Triode Control */ 276 CPCAP_REG_GREENC, /* Green Triode Control */ 277 CPCAP_REG_BLUEC, /* Blue Triode Control */ 278 CPCAP_REG_CFC, /* Camera Flash Control */ 279 CPCAP_REG_ABC, /* Adaptive Boost Control */ 280 CPCAP_REG_BLEDC, /* Bluetooth LED Control */ 281 CPCAP_REG_CLEDC, /* Camera Privacy LED Control */ 282 283 CPCAP_REG_OW1C, /* One Wire 1 Command */ 284 CPCAP_REG_OW1D, /* One Wire 1 Data */ 285 CPCAP_REG_OW1I, /* One Wire 1 Interrupt */ 286 CPCAP_REG_OW1IE, /* One Wire 1 Interrupt Enable */ 287 CPCAP_REG_OW1, /* One Wire 1 Control */ 288 CPCAP_REG_OW2C, /* One Wire 2 Command */ 289 CPCAP_REG_OW2D, /* One Wire 2 Data */ 290 CPCAP_REG_OW2I, /* One Wire 2 Interrupt */ 291 CPCAP_REG_OW2IE, /* One Wire 2 Interrupt Enable */ 292 CPCAP_REG_OW2, /* One Wire 2 Control */ 293 CPCAP_REG_OW3C, /* One Wire 3 Command */ 294 CPCAP_REG_OW3D, /* One Wire 3 Data */ 295 CPCAP_REG_OW3I, /* One Wire 3 Interrupt */ 296 CPCAP_REG_OW3IE, /* One Wire 3 Interrupt Enable */ 297 CPCAP_REG_OW3, /* One Wire 3 Control */ 298 CPCAP_REG_GCAIC, /* GCAI Clock Control */ 299 CPCAP_REG_GCAIM, /* GCAI GPIO Mode */ 300 CPCAP_REG_LGDIR, /* LMR GCAI GPIO Direction */ 301 CPCAP_REG_LGPU, /* LMR GCAI GPIO Pull-up */ 302 CPCAP_REG_LGPIN, /* LMR GCAI GPIO Pin */ 303 CPCAP_REG_LGMASK, /* LMR GCAI GPIO Mask */ 304 CPCAP_REG_LDEB, /* LMR Debounce Settings */ 305 CPCAP_REG_LGDET, /* LMR GCAI Detach Detect */ 306 CPCAP_REG_LMISC, /* LMR Misc Bits */ 307 CPCAP_REG_LMACE, /* LMR Mace IC Support */ 308 309 CPCAP_REG_END = CPCAP_REG_LMACE, /* End of CPCAP registers. */ 310 311 CPCAP_REG_MAX /* The largest valid register value. */ 312 = CPCAP_REG_END, 313 314 CPCAP_REG_SIZE = CPCAP_REG_MAX + 1, 315 CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2, 316 }; 317 318 enum { 319 CPCAP_IOCTL_NUM_TEST__START, 320 CPCAP_IOCTL_NUM_TEST_READ_REG, 321 CPCAP_IOCTL_NUM_TEST_WRITE_REG, 322 CPCAP_IOCTL_NUM_TEST__END, 323 324 CPCAP_IOCTL_NUM_ADC__START, 325 CPCAP_IOCTL_NUM_ADC_PHASE, 326 CPCAP_IOCTL_NUM_ADC__END, 327 328 CPCAP_IOCTL_NUM_BATT__START, 329 CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, 330 CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, 331 CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, 332 CPCAP_IOCTL_NUM_BATT_ATOD_READ, 333 CPCAP_IOCTL_NUM_BATT__END, 334 335 CPCAP_IOCTL_NUM_UC__START, 336 CPCAP_IOCTL_NUM_UC_MACRO_START, 337 CPCAP_IOCTL_NUM_UC_MACRO_STOP, 338 CPCAP_IOCTL_NUM_UC_GET_VENDOR, 339 CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, 340 CPCAP_IOCTL_NUM_UC__END, 341 342 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD 343 CPCAP_IOCTL_NUM_RTC__START, 344 CPCAP_IOCTL_NUM_RTC_COUNT, 345 CPCAP_IOCTL_NUM_RTC__END, 346 #endif 347 348 CPCAP_IOCTL_NUM_ACCY__START, 349 CPCAP_IOCTL_NUM_ACCY_WHISPER, 350 CPCAP_IOCTL_NUM_ACCY__END, 351 }; 352 353 enum cpcap_irqs { 354 CPCAP_IRQ__START, /* 1st supported interrupt event */ 355 CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX, /* High Speed Clock */ 356 CPCAP_IRQ_PRIMAC, /* Primary Macro */ 357 CPCAP_IRQ_SECMAC, /* Secondary Macro */ 358 CPCAP_IRQ_LOWBPL, /* Low Battery Low Threshold */ 359 CPCAP_IRQ_SEC2PRI, /* 2nd Macro to Primary Processor */ 360 CPCAP_IRQ_LOWBPH, /* Low Battery High Threshold */ 361 CPCAP_IRQ_EOL, /* End of Life */ 362 CPCAP_IRQ_TS, /* Touchscreen */ 363 CPCAP_IRQ_ADCDONE, /* ADC Conversion Complete */ 364 CPCAP_IRQ_HS, /* Headset */ 365 CPCAP_IRQ_MB2, /* Mic Bias2 */ 366 CPCAP_IRQ_VBUSOV, /* Overvoltage Detected */ 367 CPCAP_IRQ_RVRS_CHRG, /* Reverse Charge */ 368 CPCAP_IRQ_CHRG_DET, /* Charger Detected */ 369 CPCAP_IRQ_IDFLOAT, /* ID Float */ 370 CPCAP_IRQ_IDGND, /* ID Ground */ 371 372 CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX, /* SE1 Detector */ 373 CPCAP_IRQ_SESSEND, /* Session End */ 374 CPCAP_IRQ_SESSVLD, /* Session Valid */ 375 CPCAP_IRQ_VBUSVLD, /* VBUS Valid */ 376 CPCAP_IRQ_CHRG_CURR1, /* Charge Current Monitor (20mA) */ 377 CPCAP_IRQ_CHRG_CURR2, /* Charge Current Monitor (250mA) */ 378 CPCAP_IRQ_RVRS_MODE, /* Reverse Current Limit */ 379 CPCAP_IRQ_ON, /* On Signal */ 380 CPCAP_IRQ_ON2, /* On 2 Signal */ 381 CPCAP_IRQ_CLK, /* 32k Clock Transition */ 382 CPCAP_IRQ_1HZ, /* 1Hz Tick */ 383 CPCAP_IRQ_PTT, /* Push To Talk */ 384 CPCAP_IRQ_SE0CONN, /* SE0 Condition */ 385 CPCAP_IRQ_CHRG_SE1B, /* CHRG_SE1B Pin */ 386 CPCAP_IRQ_UART_ECHO_OVERRUN, /* UART Buffer Overflow */ 387 CPCAP_IRQ_EXTMEMHD, /* External MEMHOLD */ 388 389 CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX, /* Warm Start */ 390 CPCAP_IRQ_SYSRSTR, /* System Restart */ 391 CPCAP_IRQ_SOFTRST, /* Soft Reset */ 392 CPCAP_IRQ_DIEPWRDWN, /* Die Temperature Powerdown */ 393 CPCAP_IRQ_DIETEMPH, /* Die Temperature High */ 394 CPCAP_IRQ_PC, /* Power Cut */ 395 CPCAP_IRQ_OFLOWSW, /* Stopwatch Overflow */ 396 CPCAP_IRQ_TODA, /* TOD Alarm */ 397 CPCAP_IRQ_OPT_SEL_DTCH, /* Detach Detect */ 398 CPCAP_IRQ_OPT_SEL_STATE, /* State Change */ 399 CPCAP_IRQ_ONEWIRE1, /* Onewire 1 Block */ 400 CPCAP_IRQ_ONEWIRE2, /* Onewire 2 Block */ 401 CPCAP_IRQ_ONEWIRE3, /* Onewire 3 Block */ 402 CPCAP_IRQ_UCRESET, /* Microcontroller Reset */ 403 CPCAP_IRQ_PWRGOOD, /* BP Turn On */ 404 CPCAP_IRQ_USBDPLLCLK, /* USB DPLL Status */ 405 406 CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX, /* DP Line */ 407 CPCAP_IRQ_DMI, /* DM Line */ 408 CPCAP_IRQ_UCBUSY, /* Microcontroller Busy */ 409 CPCAP_IRQ_GCAI_CURR1, /* Charge Current Monitor (65mA) */ 410 CPCAP_IRQ_GCAI_CURR2, /* Charge Current Monitor (600mA) */ 411 CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR,/* SLIMbus Retransmit Error */ 412 CPCAP_IRQ_BATTDETB, /* Battery Presence Detected */ 413 CPCAP_IRQ_PRIHALT, /* Primary Microcontroller Halt */ 414 CPCAP_IRQ_SECHALT, /* Secondary Microcontroller Halt */ 415 CPCAP_IRQ_CC_CAL, /* CC Calibration */ 416 417 CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX, /* Prim ROM Rd Macro Int */ 418 CPCAP_IRQ_UC_PRIRAMW, /* Primary RAM Write Macro Int */ 419 CPCAP_IRQ_UC_PRIRAMR, /* Primary RAM Read Macro Int */ 420 CPCAP_IRQ_UC_USEROFF, /* USEROFF Macro Interrupt */ 421 CPCAP_IRQ_UC_PRIMACRO_4, /* Primary Macro 4 Interrupt */ 422 CPCAP_IRQ_UC_PRIMACRO_5, /* Primary Macro 5 Interrupt */ 423 CPCAP_IRQ_UC_PRIMACRO_6, /* Primary Macro 6 Interrupt */ 424 CPCAP_IRQ_UC_PRIMACRO_7, /* Primary Macro 7 Interrupt */ 425 CPCAP_IRQ_UC_PRIMACRO_8, /* Primary Macro 8 Interrupt */ 426 CPCAP_IRQ_UC_PRIMACRO_9, /* Primary Macro 9 Interrupt */ 427 CPCAP_IRQ_UC_PRIMACRO_10, /* Primary Macro 10 Interrupt */ 428 CPCAP_IRQ_UC_PRIMACRO_11, /* Primary Macro 11 Interrupt */ 429 CPCAP_IRQ_UC_PRIMACRO_12, /* Primary Macro 12 Interrupt */ 430 CPCAP_IRQ_UC_PRIMACRO_13, /* Primary Macro 13 Interrupt */ 431 CPCAP_IRQ_UC_PRIMACRO_14, /* Primary Macro 14 Interrupt */ 432 CPCAP_IRQ_UC_PRIMACRO_15, /* Primary Macro 15 Interrupt */ 433 CPCAP_IRQ__NUM /* Number of allocated events */ 434 }; 435 436 enum cpcap_adc_bank0 { 437 CPCAP_ADC_AD0_BATTDETB, 438 CPCAP_ADC_BATTP, 439 CPCAP_ADC_VBUS, 440 CPCAP_ADC_AD3, 441 CPCAP_ADC_BPLUS_AD4, 442 CPCAP_ADC_CHG_ISENSE, 443 CPCAP_ADC_BATTI_ADC, 444 CPCAP_ADC_USB_ID, 445 446 CPCAP_ADC_BANK0_NUM, 447 }; 448 449 enum cpcap_adc_bank1 { 450 CPCAP_ADC_AD8, 451 CPCAP_ADC_AD9, 452 CPCAP_ADC_LICELL, 453 CPCAP_ADC_HV_BATTP, 454 CPCAP_ADC_TSX1_AD12, 455 CPCAP_ADC_TSX2_AD13, 456 CPCAP_ADC_TSY1_AD14, 457 CPCAP_ADC_TSY2_AD15, 458 459 CPCAP_ADC_BANK1_NUM, 460 }; 461 462 enum cpcap_adc_format { 463 CPCAP_ADC_FORMAT_RAW, 464 CPCAP_ADC_FORMAT_PHASED, 465 CPCAP_ADC_FORMAT_CONVERTED, 466 }; 467 468 enum cpcap_adc_timing { 469 CPCAP_ADC_TIMING_IMM, 470 CPCAP_ADC_TIMING_IN, 471 CPCAP_ADC_TIMING_OUT, 472 }; 473 474 enum cpcap_adc_type { 475 CPCAP_ADC_TYPE_BANK_0, 476 CPCAP_ADC_TYPE_BANK_1, 477 CPCAP_ADC_TYPE_BATT_PI, 478 }; 479 480 enum cpcap_macro { 481 CPCAP_MACRO_ROMR, 482 CPCAP_MACRO_RAMW, 483 CPCAP_MACRO_RAMR, 484 CPCAP_MACRO_USEROFF, 485 CPCAP_MACRO_4, 486 CPCAP_MACRO_5, 487 CPCAP_MACRO_6, 488 CPCAP_MACRO_7, 489 CPCAP_MACRO_8, 490 CPCAP_MACRO_9, 491 CPCAP_MACRO_10, 492 CPCAP_MACRO_11, 493 CPCAP_MACRO_12, 494 CPCAP_MACRO_13, 495 CPCAP_MACRO_14, 496 CPCAP_MACRO_15, 497 498 CPCAP_MACRO__END, 499 }; 500 501 enum cpcap_vendor { 502 CPCAP_VENDOR_ST, 503 CPCAP_VENDOR_TI, 504 }; 505 506 enum cpcap_revision { 507 CPCAP_REVISION_1_0 = 0x08, 508 CPCAP_REVISION_1_1 = 0x09, 509 CPCAP_REVISION_2_0 = 0x10, 510 CPCAP_REVISION_2_1 = 0x11, 511 }; 512 513 enum cpcap_batt_usb_model { 514 CPCAP_BATT_USB_MODEL_NONE, 515 CPCAP_BATT_USB_MODEL_USB, 516 CPCAP_BATT_USB_MODEL_FACTORY, 517 }; 518 519 struct cpcap_spi_init_data { 520 enum cpcap_reg reg; 521 unsigned short data; 522 }; 523 524 struct cpcap_adc_ato { 525 unsigned short ato_in; 526 unsigned short atox_in; 527 unsigned short adc_ps_factor_in; 528 unsigned short atox_ps_factor_in; 529 unsigned short ato_out; 530 unsigned short atox_out; 531 unsigned short adc_ps_factor_out; 532 unsigned short atox_ps_factor_out; 533 }; 534 535 struct cpcap_batt_data { 536 int status; 537 int health; 538 int present; 539 int capacity; 540 int batt_volt; 541 int batt_temp; 542 }; 543 544 struct cpcap_batt_ac_data { 545 int online; 546 }; 547 548 struct cpcap_batt_usb_data { 549 int online; 550 int current_now; 551 enum cpcap_batt_usb_model model; 552 }; 553 554 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD 555 struct cpcap_rtc_time_cnt { 556 struct rtc_time time; 557 unsigned short count; 558 }; 559 #endif 560 struct cpcap_device; 561 562 #ifdef __KERNEL__ 563 struct cpcap_platform_data { 564 struct cpcap_spi_init_data *init; 565 int init_len; 566 unsigned short *regulator_mode_values; 567 unsigned short *regulator_off_mode_values; 568 struct regulator_init_data *regulator_init; 569 struct cpcap_adc_ato *adc_ato; 570 void (*ac_changed)(struct power_supply *, 571 struct cpcap_batt_ac_data *); 572 void (*batt_changed)(struct power_supply *, 573 struct cpcap_batt_data *); 574 void (*usb_changed)(struct power_supply *, 575 struct cpcap_batt_usb_data *); 576 u16 hwcfg[CPCAP_HWCFG_NUM]; 577 }; 578 579 struct cpcap_whisper_pdata { 580 unsigned int data_gpio; 581 unsigned int pwr_gpio; 582 unsigned char uartmux; 583 }; 584 585 struct cpcap_adc_request { 586 enum cpcap_adc_format format; 587 enum cpcap_adc_timing timing; 588 enum cpcap_adc_type type; 589 int status; 590 int result[CPCAP_ADC_BANK0_NUM]; 591 void (*callback)(struct cpcap_device *, void *); 592 void *callback_param; 593 594 /* Used in case of sync requests */ 595 struct completion completion; 596 }; 597 #endif 598 599 struct cpcap_adc_us_request { 600 enum cpcap_adc_format format; 601 enum cpcap_adc_timing timing; 602 enum cpcap_adc_type type; 603 int status; 604 int result[CPCAP_ADC_BANK0_NUM]; 605 }; 606 607 struct cpcap_adc_phase { 608 signed char offset_batti; 609 unsigned char slope_batti; 610 signed char offset_chrgi; 611 unsigned char slope_chrgi; 612 signed char offset_battp; 613 unsigned char slope_battp; 614 signed char offset_bp; 615 unsigned char slope_bp; 616 signed char offset_battt; 617 unsigned char slope_battt; 618 signed char offset_chrgv; 619 unsigned char slope_chrgv; 620 }; 621 622 struct cpcap_regacc { 623 unsigned short reg; 624 unsigned short value; 625 unsigned short mask; 626 }; 627 628 struct cpcap_whisper_request { 629 unsigned int cmd; 630 char dock_id[CPCAP_WHISPER_ID_SIZE]; 631 char dock_prop[CPCAP_WHISPER_PROP_SIZE]; 632 }; 633 634 /* 635 * Gets the contents of the specified cpcap register. 636 * 637 * INPUTS: The register number in the cpcap driver's format. 638 * 639 * OUTPUTS: The command writes the register data back to user space at the 640 * location specified, or it may return an error code. 641 */ 642 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD 643 #define CPCAP_IOCTL_GET_RTC_TIME_COUNTER \ 644 _IOR(0, CPCAP_IOCTL_NUM_RTC_COUNT, struct cpcap_rtc_time_cnt) 645 #endif 646 647 #define CPCAP_IOCTL_TEST_READ_REG \ 648 _IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*) 649 650 /* 651 * Writes the specifed cpcap register. 652 * 653 * This function writes the specified cpcap register with the specified 654 * data. 655 * 656 * INPUTS: The register number in the cpcap driver's format and the data to 657 * write to that register. 658 * 659 * OUTPUTS: The command has no output other than the returned error code for 660 * the ioctl() call. 661 */ 662 #define CPCAP_IOCTL_TEST_WRITE_REG \ 663 _IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*) 664 665 #define CPCAP_IOCTL_ADC_PHASE \ 666 _IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*) 667 668 #define CPCAP_IOCTL_BATT_DISPLAY_UPDATE \ 669 _IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*) 670 671 #define CPCAP_IOCTL_BATT_ATOD_ASYNC \ 672 _IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*) 673 674 #define CPCAP_IOCTL_BATT_ATOD_SYNC \ 675 _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*) 676 677 #define CPCAP_IOCTL_BATT_ATOD_READ \ 678 _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*) 679 680 681 #define CPCAP_IOCTL_UC_MACRO_START \ 682 _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro) 683 684 #define CPCAP_IOCTL_UC_MACRO_STOP \ 685 _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro) 686 687 #define CPCAP_IOCTL_UC_GET_VENDOR \ 688 _IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor) 689 690 #define CPCAP_IOCTL_UC_SET_TURBO_MODE \ 691 _IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short) 692 693 #define CPCAP_IOCTL_ACCY_WHISPER \ 694 _IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, struct cpcap_whisper_request*) 695 696 #ifdef __KERNEL__ 697 struct cpcap_device { 698 struct spi_device *spi; 699 enum cpcap_vendor vendor; 700 enum cpcap_revision revision; 701 void *keydata; 702 struct platform_device *regulator_pdev[CPCAP_NUM_REGULATORS]; 703 void *irqdata; 704 void *adcdata; 705 void *battdata; 706 void *ucdata; 707 void *accydata; 708 void (*h2w_new_state)(int); 709 }; 710 711 static inline void cpcap_set_keydata(struct cpcap_device *cpcap, void *data) 712 { 713 cpcap->keydata = data; 714 } 715 716 static inline void *cpcap_get_keydata(struct cpcap_device *cpcap) 717 { 718 return cpcap->keydata; 719 } 720 721 int cpcap_regacc_write(struct cpcap_device *cpcap, enum cpcap_reg reg, 722 unsigned short value, unsigned short mask); 723 724 int cpcap_regacc_read(struct cpcap_device *cpcap, enum cpcap_reg reg, 725 unsigned short *value_ptr); 726 727 int cpcap_regacc_init(struct cpcap_device *cpcap); 728 729 void cpcap_broadcast_key_event(struct cpcap_device *cpcap, 730 unsigned int code, int value); 731 732 int cpcap_irq_init(struct cpcap_device *cpcap); 733 734 void cpcap_irq_shutdown(struct cpcap_device *cpcap); 735 736 int cpcap_irq_register(struct cpcap_device *cpcap, enum cpcap_irqs irq, 737 void (*cb_func) (enum cpcap_irqs, void *), void *data); 738 739 int cpcap_irq_free(struct cpcap_device *cpcap, enum cpcap_irqs irq); 740 741 int cpcap_irq_get_data(struct cpcap_device *cpcap, enum cpcap_irqs irq, 742 void **data); 743 744 int cpcap_irq_clear(struct cpcap_device *cpcap, enum cpcap_irqs int_event); 745 746 int cpcap_irq_mask(struct cpcap_device *cpcap, enum cpcap_irqs int_event); 747 748 int cpcap_irq_unmask(struct cpcap_device *cpcap, enum cpcap_irqs int_event); 749 750 int cpcap_irq_mask_get(struct cpcap_device *cpcap, enum cpcap_irqs int_event); 751 752 int cpcap_irq_sense(struct cpcap_device *cpcap, enum cpcap_irqs int_event, 753 unsigned char clear); 754 755 #ifdef CONFIG_PM 756 int cpcap_irq_suspend(struct cpcap_device *cpcap); 757 758 int cpcap_irq_resume(struct cpcap_device *cpcap); 759 #endif 760 761 int cpcap_adc_sync_read(struct cpcap_device *cpcap, 762 struct cpcap_adc_request *request); 763 764 int cpcap_adc_async_read(struct cpcap_device *cpcap, 765 struct cpcap_adc_request *request); 766 767 void cpcap_adc_phase(struct cpcap_device *cpcap, struct cpcap_adc_phase *phase); 768 769 void cpcap_batt_set_ac_prop(struct cpcap_device *cpcap, int online); 770 771 void cpcap_batt_set_usb_prop_online(struct cpcap_device *cpcap, int online, 772 enum cpcap_batt_usb_model model); 773 774 void cpcap_batt_set_usb_prop_curr(struct cpcap_device *cpcap, 775 unsigned int curr); 776 777 int cpcap_uc_start(struct cpcap_device *cpcap, enum cpcap_macro macro); 778 779 int cpcap_uc_stop(struct cpcap_device *cpcap, enum cpcap_macro macro); 780 781 unsigned char cpcap_uc_status(struct cpcap_device *cpcap, 782 enum cpcap_macro macro); 783 784 int cpcap_accy_whisper(struct cpcap_device *cpcap, 785 struct cpcap_whisper_request *req); 786 787 void cpcap_accy_whisper_spdif_set_state(int state); 788 789 #define cpcap_driver_register platform_driver_register 790 #define cpcap_driver_unregister platform_driver_unregister 791 792 int cpcap_device_register(struct platform_device *pdev); 793 int cpcap_device_unregister(struct platform_device *pdev); 794 795 796 #endif /* __KERNEL__ */ 797 #endif /* _LINUX_SPI_CPCAP_H */ 798
