| /external/v8/src/mips/ |
| jump-target-mips.cc | 48 (cond == cc_always && rs.is(zero_reg) && rt.rm().is(zero_reg)) || \
49 (cond != cc_always && (!rs.is(zero_reg) || !rt.rm().is(zero_reg))))
|
| virtual-frame-mips-inl.h | 40 return MemOperand(zero_reg, 0);
47 return MemOperand(zero_reg, 0);
|
| codegen-mips-inl.h | 50 __ Branch(&entry_label_, cond, zero_reg, Operand(0));
|
| register-allocator-mips-inl.h | 49 0, // zero_reg
89 zero_reg,
|
| macro-assembler-mips.cc | 174 Ins(object, zero_reg, 0, kPageSizeBits);
291 scratch, Operand(zero_reg));
544 subu(at, zero_reg, rt.rm());
569 addiu(rd, zero_reg, j.imm32_);
571 ori(rd, zero_reg, j.imm32_);
586 addiu(rd, zero_reg, j.imm32_);
589 ori(rd, zero_reg, j.imm32_);
744 Branch(&conversion_done, eq, t8, Operand(zero_reg));
747 Or(t9, zero_reg, 0x7FFFFFFF);
754 Or(t9, zero_reg, 1)
[all...] |
| assembler-mips.cc | 81 0, // zero_reg
121 zero_reg,
405 // nop(type) == sll(zero_reg, zero_reg, type);
410 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
411 rs == static_cast<uint32_t>(ToNumber(zero_reg)) &&
872 beq(zero_reg, zero_reg, offset);
878 bgezal(zero_reg, offset);
906 GenInstrImmediate(BGTZ, rs, zero_reg, offset)
[all...] |
| macro-assembler-mips.h | 279 // ie. check if it is a sll zero_reg, zero_reg, <type> (referenced as
294 // Return <n> if we have a sll zero_reg, zero_reg, n
297 rt == static_cast<uint32_t>(ToNumber(zero_reg)) &&
298 rs == static_cast<uint32_t>(ToNumber(zero_reg)));
421 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
719 Register r1 = zero_reg, const Operand& r2 = Operand(zero_reg));
[all...] |
| full-codegen-mips.cc | 248 return MemOperand(zero_reg, 0);
315 return MemOperand(zero_reg, 0);
|
| regexp-macro-assembler-mips.cc | 400 return MemOperand(zero_reg, 0);
|
| codegen-mips.cc | 171 return MemOperand(zero_reg, 0);
181 return MemOperand(zero_reg, 0);
|
| simulator-mips.h | 142 zero_reg = 0, enumerator in enum:v8::internal::Simulator::Register
|
| assembler-mips.h | 78 return reg.code() - 2; // zero_reg and 'at' are skipped.
83 return from_code(index + 2); // zero_reg and 'at' are skipped.
129 const Register zero_reg = { 0 }; member in namespace:v8::internal
547 sll(zero_reg, zero_reg, type, true);
608 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | 139 __ ori(t0, zero_reg, 0);
193 __ addiu(v0, zero_reg, 0x7421); // 0x00007421
577 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
585 __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
589 __ Addu(t0, zero_reg, Operand(1));
1171 __ ctc1(zero_reg, FCSR);
1190 __ ctc1(zero_reg, FCSR); \
1196 __ ctc1(zero_reg, FCSR); \
[all...] |
