| /external/proguard/src/proguard/optimize/info/ |
| SuperInvocationMarker.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
47 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
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| VariableUsageMarker.java | 26 import proguard.classfile.instruction.*;
27 import proguard.classfile.instruction.visitor.InstructionVisitor;
81 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
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| /external/valgrind/main/none/tests/x86/ |
| faultstatus.stderr.exp | 6 Test 5: disInstr: unhandled instruction bytes: 0x........ 0x........ 0x........ 0x........
|
| /external/webkit/LayoutTests/fast/encoding/ |
| css-charset-default-expected.txt | 3 Stylesheet 1 (inherit document charset using xml-stylesheet processing instruction): SU???SS
|
| /external/proguard/src/proguard/classfile/util/ |
| DynamicClassReferenceInitializer.java | 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
87 private final Instruction[] CONSTANT_CLASS_FOR_NAME_INSTRUCTIONS = new Instruction[]
94 private final Instruction[] CLASS_FOR_NAME_CAST_INSTRUCTIONS = new Instruction[]
118 private final Instruction[] DOT_CLASS_JAVAC_INSTRUCTIONS = new Instruction[]
141 private final Instruction[] DOT_CLASS_JIKES_INSTRUCTIONS = new Instruction[]
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| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| InsnFormat.java | 29 * Base class for all instruction format handlers. Instruction format
37 * dump, of the given instruction. The instruction must be of this
40 * @param insn {@code non-null;} the instruction
67 * Returns the string form of the arguments to the given instruction.
68 * The instruction must be of this instance's format. If the instruction
74 * @param insn {@code non-null;} the instruction
80 * Returns the associated comment for the given instruction, if any
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| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 26 class Instruction;
41 /// FastISel - This is a fast-path instruction selection class that
60 /// getLastLocalValue - Return the position of the last instruction
64 /// setLastLocalValue - Update the position of the last instruction
76 /// SelectInstruction - Do "fast" instruction selection for the given
77 /// LLVM IR instruction, and append generated machine instructions to
80 bool SelectInstruction(const Instruction *I);
82 /// SelectOperator - Do "fast" instruction selection for the given
83 /// LLVM IR operator (Instruction or ConstantExpr), and append
104 /// vreg is being provided by the specified load instruction. If possible
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| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | 10 // This file contains the actual instruction interpreter.
45 // Binary Instruction Implementations
59 dbgs() << "Unhandled type for FAdd instruction: " << *Ty << "\n";
70 dbgs() << "Unhandled type for FSub instruction: " << *Ty << "\n";
81 dbgs() << "Unhandled type for FMul instruction: " << *Ty << "\n";
92 dbgs() << "Unhandled type for FDiv instruction: " << *Ty << "\n";
107 dbgs() << "Unhandled type for Rem instruction: " << *Ty << "\n";
295 dbgs() << "Unhandled type for FCmp EQ instruction: " << *Ty << "\n";
309 dbgs() << "Unhandled type for FCmp NE instruction: " << *Ty << "\n";
322 dbgs() << "Unhandled type for FCmp LE instruction: " << *Ty << "\n"
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| /external/v8/src/mips/ |
| simulator-mips.h | 182 // instruction.
244 void Format(Instruction* instr, const char* format);
252 inline uint16_t ReadHU(int32_t addr, Instruction* instr);
253 inline int16_t ReadH(int32_t addr, Instruction* instr);
255 inline void WriteH(int32_t addr, uint16_t value, Instruction* instr);
256 inline void WriteH(int32_t addr, int16_t value, Instruction* instr);
258 inline int ReadW(int32_t addr, Instruction* instr);
259 inline void WriteW(int32_t addr, int value, Instruction* instr);
261 inline double ReadD(int32_t addr, Instruction* instr);
262 inline void WriteD(int32_t addr, double value, Instruction* instr)
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| /prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/include/ |
| dis-asm.h | 23 The opcode library (libopcodes.a) provides instruction decoders for
24 a large variety of instruction sets, callable with an identical
25 interface, for making instruction-processing programs more independent
26 of the instruction set being processed. */
42 dis_noninsn, /* Not a valid instruction */
43 dis_nonbranch, /* Not a branch instruction */
48 dis_dref, /* Data reference instruction */
49 dis_dref2 /* Two data references in instruction */
52 /* This struct is passed into the instruction decoding routine,
55 for passing information into the instruction decoders (such as th
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| /external/llvm/include/llvm/Support/ |
| CallSite.h | 43 typename InstrTy = const Instruction,
57 /// will create an appropriate call site for a Call or Invoke instruction, but
63 if (II->getOpcode() == Instruction::Call)
65 else if (II->getOpcode() == Instruction::Invoke)
73 /// it also could signify a NULL Instruction pointer.
87 assert(getInstruction() && "Not a call or invoke instruction!");
101 assert(getInstruction() && "Not a call or invoke instruction!");
118 assert(getInstruction() && "Not a call or invoke instruction!");
126 assert(getInstruction() && "Not a call or invoke instruction!");
139 assert(getInstruction() && "Not a call or invoke instruction!");
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| /dalvik/dx/src/com/android/dx/ssa/ |
| SsaInsn.java | 23 * An instruction in SSA form
188 * instruction, or null if no local variable assignment occurs. This
206 * used as sources for this instruction.
220 * @return {@code non-null;} a ROP representation of this instruction, with
241 * move-exception) instruction
248 * @return true if this is a move-exception instruction.
256 * @return true if this instruction can throw.
272 * Any non-phi move instruction
273 * @param insn {@code non-null;} the instruction to visit
279 * @param insn {@code non-null;} the instruction to visi
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| /dalvik/vm/mterp/armv5te/ |
| header.S | 60 r7 rINST first 16-bit code unit of current instruction
61 r8 rIBASE interpreted instruction base pointer, used for computed goto
64 one instruction to make instruction-counting easier. They MUST NOT alter
104 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
109 * Fetch the next instruction from the specified offset. Advances rPC
110 * to point to the next instruction. "_count" is in 16-bit code units.
130 * Fetch the next instruction from an offset specified by _reg. Updates
131 * rPC to point to the next instruction. "_reg" must specify the distance
158 * Put the instruction's opcode field into the specified register
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| OP_CONST_CLASS.S | 16 GOTO_OPCODE(ip) @ jump to next instruction
35 GOTO_OPCODE(ip) @ jump to next instruction
|
| /external/chromium/sdch/open-vcdiff/src/ |
| instruction_map.h | 36 // optimizes for fast encoding, that is, for taking a delta instruction
37 // inst (also known as instruction type), size, and mode and arriving at
44 // to create the instruction->opcode mappings. The caller *must* have
47 // max_mode is the maximum value for the mode of a COPY instruction.
55 // instruction and NOOP for its second instruction (or vice versa.)
74 // lookupFirstOpcode), finds an opcode that has the same first instruction as
76 // instruction.
128 // VCD_COPY being the last instruction type. The inst+mode values are:
143 // for each possible first instruction size (size1) in the code table
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| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpander.h | 37 std::map<std::pair<const SCEV *, Instruction *>, AssertingVH<Value> >
47 /// returns the add instruction that adds one to the phi for {0,+,1}<L>,
59 Instruction *IVIncInsertPos;
97 Value *expandCodeFor(const SCEV *SH, Type *Ty, Instruction *I);
100 void setIVIncInsertPos(const Loop *L, Instruction *Pos) {
131 /// if the instruction that had been serving as the insertion point may
142 Value *InsertBinop(Instruction::BinaryOps Opcode, Value *LHS, Value *RHS);
149 Instruction::CastOps Op,
171 /// isInsertedInstruction - Return true if the specified instruction was
173 /// instruction
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| /external/webkit/Source/JavaScriptCore/assembler/ |
| AssemblerBufferWithConstantPool.h | 49 into the instruction stream - protected by a jump instruction from the
52 The flush mechanism is called when no space remain to insert the next instruction
54 have to be inserted into the instruction stream (Assembler Buffer):
59 - barrierSize: size of jump instruction in bytes which protects the
62 - maxInstructionSize: maximum length of a machine instruction in bytes
68 patch the 'load' instruction with the index of the constant in the
69 constant pool and return the patched instruction.
72 patch the a PC relative load instruction at 'loadAddr' address with the
75 constant (which is stored previously in the load instruction itself)
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 19 // constructs that are not exposed before lowering and instruction selection.
108 const char *getPassName() const { return "Machine Instruction LICM"; }
144 /// HoistPostRA - When an instruction is found to only use loop invariant
145 /// operands that is safe to hoist, this instruction is called to do the
149 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
159 /// IsLICMCandidate - Returns true if the instruction may be a suitable
160 /// candidate for LICM. e.g. If the instruction is a call, then it's
164 /// IsLoopInvariantInst - Returns true if the instruction is loop
167 /// and the instruction is hoistable.
184 /// check if hoisting an instruction of the given cost matrix can cause hig
[all...] |
| TargetInstrInfoImpl.cpp | 1 //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
37 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
65 // No idea how to commute this instruction. Target should implement its own.
83 // Must be two address instruction!
85 "Expecting a two-address instruction!");
91 // Create a new instruction.
117 /// operand indices that would swap value. Return true if the instruction
184 "Instruction cannot be duplicated");
188 // If the COPY instruction in MI can be folded to a stack operation, return
192 assert(MI->isCopy() && "MI must be a COPY instruction");
[all...] |
| /dalvik/docs/ |
| dalvik-constraints.html | 201 The index of instruction <code>n+1</code> must equal the index of
202 instruction <code>n</code> plus the length of instruction
217 The last instruction in the <code>insns</code> array must end at index
247 All targets of a <code>packed-switch</code> instruction must be
263 All targets of a <code>sparse-switch</code> instruction must be
383 instruction must be a valid index into the method constant pool. The
400 instruction must be a valid index into the method constant pool.
450 instruction must be less than <code>256</code>.
464 The <code>new</code> instruction must not refer to array classes
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 57 if (I->getOpcode() == Instruction::LShr && !I->isExact()) {
62 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
99 Instruction *InstCombiner::visitMul(BinaryOperator &I) {
116 if (SI->getOpcode() == Instruction::Shl)
167 if (Instruction *R = FoldOpIntoSelect(I, SI))
171 if (Instruction *NV = FoldOpIntoPhi(I))
185 (BO->getOpcode() != Instruction::UDiv &&
186 BO->getOpcode() != Instruction::SDiv)) {
193 (BO->getOpcode() == Instruction::UDiv ||
194 BO->getOpcode() == Instruction::SDiv))
[all...] |
| /dalvik/dx/src/com/android/dx/cf/code/ |
| BasicBlocker.java | 44 * middle of an instruction or is a definitely-dead opcode
56 * {@code non-null, sparse;} for each instruction offset to a branch of
57 * some sort, the list of targets for that instruction
62 * {@code non-null, sparse;} for each instruction offset to a throwing
63 * instruction, the list of exception handlers for that instruction
206 * possibility of throwing, so this instruction needs to
226 * only the jsr instruction) but is otherwise treated
228 * target and next instruction begin new blocks.)
285 * instruction at the end of this block, if any. I
[all...] |
| /external/qemu/ |
| dis-asm.h | 4 The opcode library (libopcodes.a) provides instruction decoders for
5 a large variety of instruction sets, callable with an identical
6 interface, for making instruction-processing programs more independent
7 of the instruction set being processed. */
99 /* Nonzero if MACH has the v9 instruction set. */
237 dis_noninsn, /* Not a valid instruction */
238 dis_nonbranch, /* Not a branch instruction */
243 dis_dref, /* Data reference instruction */
244 dis_dref2 /* Two data references in instruction */
247 /* This struct is passed into the instruction decoding routine
[all...] |
| /dalvik/dx/tests/086-ssa-edge-split/ |
| Blort.java | 56 * Presently, any basic block ending in an instruction with
58 * only to the block between the switch instruction and the return
|
| /dalvik/vm/compiler/codegen/arm/ |
| README.txt | 36 - Factory.c (low-level routines for instruction selections)
37 - Gen.c (invoke the ISA-specific instruction selection routines)
|
