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  /external/llvm/test/CodeGen/CellSPU/
vec_const.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
2 ; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
intrinsics_logical.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
mul_ops.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
shuffles.ll 1 ; RUN: llc -O1 --march=cellspu < %s | FileCheck %s
stores.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
17 ; RUN: llc < %s -march=cellspu | FileCheck %s
dp_farith.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
icmp64.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
sp_farith.ll 1 ; RUN: llc < %s -march=cellspu -enable-unsafe-fp-math > %t1.s
trunc.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
intrinsics_float.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
nand.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
vecinsert.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
eqv.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
extract_elt.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
intrinsics_branch.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
rotate_ops.ll 1 ; RUN: llc < %s -march=cellspu -o %t1.s
shift_ops.ll 1 ; RUN: llc < %s -march=cellspu > %t1.s
  /external/llvm/lib/Support/
Triple.cpp 29 case cellspu: return "cellspu";
63 case cellspu: return "spu";
141 if (Name == "cellspu")
142 return cellspu;
281 else if (ArchName == "spu" || ArchName == "cellspu")
282 return cellspu;
  /external/llvm/include/llvm/ADT/
Triple.h 52 cellspu, // CellSPU: spu, cellspu enumerator in enum:llvm::Triple::ArchType
  /external/llvm/lib/Target/CellSPU/
SPUInstrInfo.h 10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
SPUSubtarget.cpp 10 // This file implements the CellSPU-specific subclass of TargetSubtargetInfo.
SPUNodes.td 1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
10 // Type profiles and SelectionDAG nodes used by CellSPU
  /external/llvm/utils/lit/lit/ExampleTests/LLVM.InTree/test/
site.exp 5 set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend"
  /external/llvm/utils/lit/lit/ExampleTests/LLVM.OutOfTree/obj/test/
site.exp 5 set TARGETS_TO_BUILD "X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend MSIL CppBackend"
  /external/llvm/
CMakeLists.txt 71 CellSPU

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