| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 192 ((vecVT == MVT::v2i64) &&
602 case MVT::v2i64:
716 } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
728 } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
740 } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
824 MVT::v2i64,
837 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
905 * \note This code could also be used to implement v2i64 shl.
[all...] |
| SPUISelLowering.h | 79 //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
|
| SPUOperands.td | 389 // immediate constant load for v2i64 vectors.
401 // immediate constant load for v2i64 vectors.
413 // immediate constant load for v2i64 vectors.
|
| SPURegisterInfo.td | 182 def VECREG : RegisterClass<"SPU", [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], 128,
|
| SPUISelLowering.cpp | 396 addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
[all...] |
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 127 case MVT::v2i64: return "v2i64";
174 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);
|
| /external/llvm/test/CodeGen/ARM/ |
| vshiftins.ll | 71 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
155 declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
|
| vld1.ll | 116 %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
130 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
|
| vst1.ll | 116 call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
130 declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind
|
| vmul.ll | 206 %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
266 %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
315 %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
355 %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
361 declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
365 declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
|
| vsra.ll | 278 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
318 %tmp3 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
336 declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
341 declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| ARMRegisterInfo.td | 280 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
289 def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
296 def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 67 v2i64 = 25, // 2 x i64 enumerator in enum:llvm::MVT::SimpleValueType
203 case v2i64:
235 case v2i64:
275 case v2i64:
358 if (NumElements == 2) return MVT::v2i64;
482 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
|
| ValueTypes.td | 48 def v2i64 : ValueType<128, 25>; // 2 x i64 vector value
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86RegisterInfo.td | 453 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.td | 59 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 189 def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q,
|
| SystemZISelDAGToDAG.cpp | 614 ResVT = MVT::v2i64;
619 ResVT = MVT::v2i64;
701 ResVT = MVT::v2i64;
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 82 case MVT::v2i64: return "MVT::v2i64";
|
| /external/llvm/include/llvm/ |
| Intrinsics.td | 131 def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
|
| /external/clang/utils/ABITest/ |
| ABITestGen.py | 462 action="store", type=str, default='v2i16, v1i64, v2i32, v4i16, v8i8, v2f32, v2i64, v4i32, v8i16, v16i8, v2f64, v4f32, v16f32', metavar="N")
|
