| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 66 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
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| LiveVariables.h | 186 /// register which is used in a PHI node. We map that to the BB the vreg
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| ScheduleDAG.h | 253 bool isVRegCycle : 1; // May use and def the same vreg.
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| /external/llvm/lib/CodeGen/ |
| Spiller.cpp | 118 // Create a new vreg & interval for this instr.
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| ProcessImplicitDefs.cpp | 269 // Replace Reg with a new vreg that's marked implicit.
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| Splitter.cpp | 100 unsigned vreg = ls.mri->createVirtualRegister(trc); local
101 newLI = &ls.lis->getOrCreateInterval(vreg);
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| LiveVariables.cpp | 80 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
673 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
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| TwoAddressInstructionPass.cpp | [all...] |
| RegAllocFast.cpp | 826 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
847 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
[all...] |
| MachineSink.cpp | 155 // the definition of the vreg. Dwarf generator handles this although the
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| VirtRegRewriter.cpp | 89 /// rewrites vreg def/uses to use the assigned preg, but does not insert any
372 unsigned vreg)
374 AssignedPhysReg(apr), VirtReg(vreg) {}
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 329 unsigned VReg = RegInfo.createVirtualRegister(RC);
330 RegInfo.addLiveIn(VA.getLocReg(), VReg);
331 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
816 // control-flow pattern. The incoming instruction knows the destination vreg
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 212 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
214 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
324 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
325 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
326 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_x86_defs.c | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 336 unsigned VReg =
338 RegInfo.addLiveIn(VA.getLocReg(), VReg);
339 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 75 // the definition of the vreg. Dwarf generator handles this although the
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| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 622 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
633 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
634 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 310 // If Reg is live-in then update debug info to track its copy in a vreg.
324 // If this vreg is directly copied into an exported register then
439 // If this is a CopyToReg with a vreg dest, process it.
761 // Figure out which vreg this is going into. If there is no assigned vreg yet
768 // Check to see what the uses of this vreg are. If it has no uses, or more
774 // See if there is exactly one use of the vreg. If there are multiple uses,
783 "The only use of the vreg must be a use, we haven't emitted the def!");
[all...] |
| FunctionLoweringInfo.cpp | 214 /// consecutive vreg numbers and return the first assigned number.
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| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 252 // simple loop. The incoming instruction knows the destination vreg to
253 // set, the source vreg to operate over and the shift amount.
352 // destination vreg to set, the condition code register to branch on, the
432 // simple loop. The incoming instruction knows the destination vreg to
433 // set, the source vreg to operate over and the shift amount.
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/libvpx/vp8/common/ppc/ |
| loopfilter_filters_altivec.asm | 345 ;# into vector register Vreg. Trashes r0
346 .macro load_g Vreg, Gptr
348 lvx \Vreg, 0, r0
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 42 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
43 MF.getRegInfo().addLiveIn(PReg, VReg);
44 return VReg;
[all...] |
| /external/llvm/ |
| CREDITS.TXT | 202 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
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| /external/webkit/Source/JavaScriptCore/jit/ |
| JIT.h | 536 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
[all...] |
