| /external/llvm/tools/macho-dump/ |
| macho-dump.cpp | 57 outs() << " ('segment_name', '";
58 outs().write_escaped(Name, /*UseHexEscapes=*/true) << "')\n";
59 outs() << " ('vm_addr', " << VMAddr << ")\n";
60 outs() << " ('vm_size', " << VMSize << ")\n";
61 outs() << " ('file_offset', " << FileOffset << ")\n";
62 outs() << " ('file_size', " << FileSize << ")\n";
63 outs() << " ('maxprot', " << MaxProt << ")\n";
64 outs() << " ('initprot', " << InitProt << ")\n";
65 outs() << " ('num_sections', " << NumSections << ")\n";
66 outs() << " ('flags', " << Flags << ")\n"
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
60 dag OutOperandList = outs;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>
[all...] |
| MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrFormats.td | 13 class InstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
18 dag OutOperandList = outs;
25 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
26 : InstXCore<outs, ins, asmstr, pattern>;
32 class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern>
33 : InstXCore<outs, ins, asmstr, pattern> {
37 class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern>
38 : InstXCore<outs, ins, asmstr, pattern> {
42 class _F2RUS<dag outs, dag ins, string asmstr, list<dag> pattern>
43 : InstXCore<outs, ins, asmstr, pattern>
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrFormats.td | 45 class InstSystemZ<bits<16> op, Format f, dag outs, dag ins> : Instruction {
53 dag OutOperandList = outs;
57 class I8<bits<8> op, Format f, dag outs, dag ins, string asmstr,
59 : InstSystemZ<0, f, outs, ins> {
67 class I12<bits<12> op, Format f, dag outs, dag ins, string asmstr,
69 : InstSystemZ<0, f, outs, ins> {
77 class I16<bits<16> op, Format f, dag outs, dag ins, string asmstr,
79 : InstSystemZ<op, f, outs, ins> {
84 class RRI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
85 : I8<op, RRForm, outs, ins, asmstr, pattern>
[all...] |
| SystemZInstrInfo.td | 71 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
74 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
96 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst)
[all...] |
| SystemZInstrFP.td | 29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrSystem.td | 17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
43 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
47 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB
[all...] |
| X86InstrFormats.td | 118 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
128 dag OutOperandList = outs;
180 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
182 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
186 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
188 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
192 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
194 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
198 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
200 : X86Inst<o, f, Imm16, outs, ins, asm>
[all...] |
| X86InstrFPStack.td | 76 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
78 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
80 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
82 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
84 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
86 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
88 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
90 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
92 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
116 def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>
[all...] |
| X86InstrControl.td | 21 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
24 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
27 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
30 def LRETL : I <0xCB, RawFrm, (outs), (ins),
32 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
34 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
36 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
42 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
44 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
46 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst)
[all...] |
| X86InstrExtension.td | 16 def CBW : I<0x98, RawFrm, (outs), (ins),
19 def CWDE : I<0x98, RawFrm, (outs), (ins),
23 def CWD : I<0x99, RawFrm, (outs), (ins),
26 def CDQ : I<0x99, RawFrm, (outs), (ins),
31 def CDQE : RI<0x98, RawFrm, (outs), (ins),
35 def CQO : RI<0x99, RawFrm, (outs), (ins),
41 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
43 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
45 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
48 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src)
[all...] |
| X86InstrShiftRotate.td | 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
45 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
52 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
54 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1)
[all...] |
| X86InstrVMX.td | 19 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
21 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
23 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
24 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
27 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
29 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
30 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
32 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
34 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
36 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src)
[all...] |
| /dalvik/dx/tests/051-dex-explicit-null/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0000
6 regs: 0003; ins: 0001; outs: 0000
|
| /dalvik/dx/tests/055-dex-explicit-throw/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0000
6 regs: 0002; ins: 0000; outs: 0000
|
| /dalvik/dx/tests/063-dex-empty-switch/ |
| expected.txt | 2 regs: 0005; ins: 0002; outs: 0000
10 regs: 0005; ins: 0002; outs: 0000
|
| /dalvik/dx/tests/111-use-null-as-array/ |
| expected.txt | 2 regs: 0002; ins: 0000; outs: 0000
8 regs: 0002; ins: 0000; outs: 0000
14 regs: 0002; ins: 0000; outs: 0000
20 regs: 0002; ins: 0000; outs: 0000
26 regs: 0002; ins: 0000; outs: 0000
32 regs: 0002; ins: 0000; outs: 0000
38 regs: 0002; ins: 0000; outs: 0000
44 regs: 0002; ins: 0000; outs: 0000
50 regs: 0002; ins: 0000; outs: 0000
56 regs: 0002; ins: 0000; outs: 000
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
77 (outs), (ins calltarget:$func, variable_ops),
80 (outs), (ins aaddr:$func, variable_ops),
85 (outs), (ins variable_ops),
103 (outs), (ins calltarget:$func, variable_ops),
106 (outs), (ins aaddr:$func, variable_ops),
111 (outs), (ins variable_ops),
135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), ""
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.td | 206 def rr32 : InstPTX<(outs RegF32:$d),
210 def ri32 : InstPTX<(outs RegF32:$d),
214 def rr64 : InstPTX<(outs RegF64:$d),
218 def ri64 : InstPTX<(outs RegF64:$d),
226 def rr32 : InstPTX<(outs RegF32:$d),
230 def ri32 : InstPTX<(outs RegF32:$d),
234 def rr64 : InstPTX<(outs RegF64:$d),
238 def ri64 : InstPTX<(outs RegF64:$d),
246 def rrr32 : InstPTX<(outs RegF32:$d),
252 def rri32 : InstPTX<(outs RegF32:$d)
[all...] |
| /dalvik/dx/tests/049-dex-instanceof/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
|
| /dalvik/dx/tests/050-dex-checkcast/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
|
| /dalvik/dx/tests/060-dex-call-static/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0001
|
| /dalvik/dx/tests/068-dex-infinite-loop/ |
| expected.txt | 2 regs: 0000; ins: 0000; outs: 0000
5 regs: 0001; ins: 0000; outs: 0000
11 regs: 0001; ins: 0000; outs: 0000
19 regs: 0001; ins: 0000; outs: 0000
|
| /dalvik/dx/tests/095-dex-const-string-jumbo/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0001
|
