1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 **************************************************************************** 11 ****************************************************************************/ 12 #ifndef _ASM_SH_HD64465_ 13 #define _ASM_SH_HD64465_ 1 14 15 #include <asm/io.h> 16 #include <asm/irq.h> 17 18 #define HD64465_REG_SRR 0x1000c 19 #define HD64465_REG_SDID 0x10010 20 #define HD64465_SDID 0x8122 21 22 #define HD64465_REG_SMSCR 0x10000 23 #define HD64465_SMSCR_PS2ST 0x4000 24 #define HD64465_SMSCR_ADCST 0x1000 25 #define HD64465_SMSCR_UARTST 0x0800 26 #define HD64465_SMSCR_SCDIST 0x0200 27 #define HD64465_SMSCR_PPST 0x0100 28 #define HD64465_SMSCR_PC0ST 0x0040 29 #define HD64465_SMSCR_PC1ST 0x0020 30 #define HD64465_SMSCR_AFEST 0x0010 31 #define HD64465_SMSCR_TM0ST 0x0008 32 #define HD64465_SMSCR_TM1ST 0x0004 33 #define HD64465_SMSCR_IRDAST 0x0002 34 #define HD64465_SMSCR_KBCST 0x0001 35 36 #define HD64465_REG_NIRR 0x15000 37 #define HD64465_REG_NIMR 0x15002 38 #define HD64465_REG_NITR 0x15004 39 40 #define HD64465_REG_TCVR1 0x16000 41 #define HD64465_REG_TCVR0 0x16002 42 #define HD64465_REG_TRVR1 0x16004 43 #define HD64465_REG_TRVR0 0x16006 44 #define HD64465_REG_TCR1 0x16008 45 #define HD64465_REG_TCR0 0x1600A 46 #define HD64465_TCR_EADT 0x10 47 #define HD64465_TCR_ETMO 0x08 48 #define HD64465_TCR_PST_MASK 0x06 49 #define HD64465_TCR_PST_1 0x06 50 #define HD64465_TCR_PST_4 0x04 51 #define HD64465_TCR_PST_8 0x02 52 #define HD64465_TCR_PST_16 0x00 53 #define HD64465_TCR_TSTP 0x01 54 #define HD64465_REG_TIRR 0x1600C 55 #define HD64465_REG_TIDR 0x1600E 56 #define HD64465_REG_PWM1CS 0x16010 57 #define HD64465_REG_PWM1LPC 0x16012 58 #define HD64465_REG_PWM1HPC 0x16014 59 #define HD64465_REG_PWM0CS 0x16018 60 #define HD64465_REG_PWM0LPC 0x1601A 61 #define HD64465_REG_PWM0HPC 0x1601C 62 63 #define HD64465_REG_ADDRA 0x1E000 64 #define HD64465_REG_ADDRB 0x1E002 65 #define HD64465_REG_ADDRC 0x1E004 66 #define HD64465_REG_ADDRD 0x1E006 67 #define HD64465_REG_ADCSR 0x1E008 68 #define HD64465_ADCSR_ADF 0x80 69 #define HD64465_ADCSR_ADST 0x40 70 #define HD64465_ADCSR_ADIS 0x20 71 #define HD64465_ADCSR_TRGE 0x10 72 #define HD64465_ADCSR_ADIE 0x08 73 #define HD64465_ADCSR_SCAN 0x04 74 #define HD64465_ADCSR_CH_MASK 0x03 75 #define HD64465_REG_ADCALCR 0x1E00A 76 #define HD64465_REG_ADCAL 0x1E00C 77 78 #define HD64465_REG_GPACR 0x14000 79 #define HD64465_REG_GPBCR 0x14002 80 #define HD64465_REG_GPCCR 0x14004 81 #define HD64465_REG_GPDCR 0x14006 82 #define HD64465_REG_GPECR 0x14008 83 #define HD64465_REG_GPADR 0x14010 84 #define HD64465_REG_GPBDR 0x14012 85 #define HD64465_REG_GPCDR 0x14014 86 #define HD64465_REG_GPDDR 0x14016 87 #define HD64465_REG_GPEDR 0x14018 88 #define HD64465_REG_GPAICR 0x14020 89 #define HD64465_REG_GPBICR 0x14022 90 #define HD64465_REG_GPCICR 0x14024 91 #define HD64465_REG_GPDICR 0x14026 92 #define HD64465_REG_GPEICR 0x14028 93 #define HD64465_REG_GPAISR 0x14040 94 #define HD64465_REG_GPBISR 0x14042 95 #define HD64465_REG_GPCISR 0x14044 96 #define HD64465_REG_GPDISR 0x14046 97 #define HD64465_REG_GPEISR 0x14048 98 99 #define HD64465_REG_PCC0ISR 0x12000 100 #define HD64465_PCCISR_PREADY 0x80 101 #define HD64465_PCCISR_PIREQ 0x80 102 #define HD64465_PCCISR_PMWP 0x40 103 #define HD64465_PCCISR_PVS2 0x20 104 #define HD64465_PCCISR_PVS1 0x10 105 #define HD64465_PCCISR_PCD_MASK 0x0c 106 #define HD64465_PCCISR_PBVD_MASK 0x03 107 #define HD64465_PCCISR_PBVD_BATGOOD 0x03 108 #define HD64465_PCCISR_PBVD_BATWARN 0x01 109 #define HD64465_PCCISR_PBVD_BATDEAD1 0x02 110 #define HD64465_PCCISR_PBVD_BATDEAD2 0x00 111 #define HD64465_REG_PCC0GCR 0x12002 112 #define HD64465_PCCGCR_PDRV 0x80 113 #define HD64465_PCCGCR_PCCR 0x40 114 #define HD64465_PCCGCR_PCCT 0x20 115 #define HD64465_PCCGCR_PVCC0 0x10 116 #define HD64465_PCCGCR_PMMOD 0x08 117 #define HD64465_PCCGCR_PPA25 0x04 118 #define HD64465_PCCGCR_PPA24 0x02 119 #define HD64465_PCCGCR_PREG 0x01 120 #define HD64465_REG_PCC0CSCR 0x12004 121 #define HD64465_PCCCSCR_PSCDI 0x80 122 #define HD64465_PCCCSCR_PSWSEL 0x40 123 #define HD64465_PCCCSCR_PIREQ 0x20 124 #define HD64465_PCCCSCR_PSC 0x10 125 #define HD64465_PCCCSCR_PCDC 0x08 126 #define HD64465_PCCCSCR_PRC 0x04 127 #define HD64465_PCCCSCR_PBW 0x02 128 #define HD64465_PCCCSCR_PBD 0x01 129 #define HD64465_REG_PCC0CSCIER 0x12006 130 #define HD64465_PCCCSCIER_PCRE 0x80 131 #define HD64465_PCCCSCIER_PIREQE_MASK 0x60 132 #define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 133 #define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 134 #define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 135 #define HD64465_PCCCSCIER_PIREQE_RISING 0x60 136 #define HD64465_PCCCSCIER_PSCE 0x10 137 #define HD64465_PCCCSCIER_PCDE 0x08 138 #define HD64465_PCCCSCIER_PRE 0x04 139 #define HD64465_PCCCSCIER_PBWE 0x02 140 #define HD64465_PCCCSCIER_PBDE 0x01 141 #define HD64465_REG_PCC0SCR 0x12008 142 #define HD64465_PCCSCR_SHDN 0x10 143 #define HD64465_PCCSCR_SWP 0x01 144 #define HD64465_REG_PCCPSR 0x1200A 145 #define HD64465_REG_PCC1ISR 0x12010 146 #define HD64465_REG_PCC1GCR 0x12012 147 #define HD64465_REG_PCC1CSCR 0x12014 148 #define HD64465_REG_PCC1CSCIER 0x12016 149 #define HD64465_REG_PCC1SCR 0x12018 150 151 #define HD64465_REG_KBCSR 0x1dc00 152 #define HD64465_KBCSR_KBCIE 0x8000 153 #define HD64465_KBCSR_KBCOE 0x4000 154 #define HD64465_KBCSR_KBDOE 0x2000 155 #define HD64465_KBCSR_KBCD 0x1000 156 #define HD64465_KBCSR_KBDD 0x0800 157 #define HD64465_KBCSR_KBCS 0x0400 158 #define HD64465_KBCSR_KBDS 0x0200 159 #define HD64465_KBCSR_KBDP 0x0100 160 #define HD64465_KBCSR_KBD_MASK 0x00ff 161 #define HD64465_REG_KBISR 0x1dc04 162 #define HD64465_KBISR_KBRDF 0x0001 163 #define HD64465_REG_MSCSR 0x1dc10 164 #define HD64465_REG_MSISR 0x1dc14 165 166 #define CONFIG_HD64465_IOBASE 0xb0000000 167 168 #define CONFIG_HD64465_IRQ 5 169 170 #define _HD64465_IO_MASK 0xf8000000 171 #define is_hd64465_addr(addr) ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK)) 172 173 #define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE 174 #define HD64465_IRQ_NUM 16 175 #define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0) 176 #define HD64465_IRQ_USB (HD64465_IRQ_BASE+1) 177 #define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2) 178 #define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3) 179 180 #define HD64465_IRQ_UART (HD64465_IRQ_BASE+5) 181 #define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6) 182 #define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7) 183 #define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8) 184 #define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9) 185 #define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10) 186 #define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11) 187 #define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12) 188 #define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13) 189 #define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14) 190 #define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15) 191 192 #define HD64465_PCC_WINDOW 0x01000000 193 194 #define HD64465_PCC0_BASE 0xb8000000 195 #define HD64465_PCC0_ATTR (HD64465_PCC0_BASE) 196 #define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW) 197 #define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW) 198 199 #define HD64465_PCC1_BASE 0xb4000000 200 #define HD64465_PCC1_ATTR (HD64465_PCC1_BASE) 201 #define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW) 202 #define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW) 203 204 #define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000) 205 #define HD64465_USB_LEN 0x1000 206 207 #define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000) 208 #define HD64465_SRAM_LEN 0x1000 209 210 #endif 211
